24 Sampling and Aliasing

24.1 In 60 Seconds

Prove the Digital Number Still Represents the Signal

Picture a pressure sensor whose stored values flatten near the top of its range. More samples cannot repair a signal that the input stage has already clipped.

An analog-to-digital converter means the part that turns a changing voltage into numbers. ADC is the short name used here. State its input range, resolution, reference, sample timing, and filter before trusting the output.

Apply known low, middle, high, over-range, and changing inputs. Keep the source value, raw code, time, reference, settings, plot, and error so another person can repeat the check.

This test covers one input path and chosen signals, not every noise source. The deeper sections develop sampling, aliasing, scaling, filtering, calibration, and uncertainty.

An ADC makes a timed digital record of a changing analog voltage. A trustworthy sample plan starts with the physical signal, limits misleading high-frequency content before conversion, samples fast enough with margin, and records the range, reference, bit depth, timestamp policy, and validation evidence that make each code meaningful.

24.2 Start With the Story

You will choose sampling and conversion settings that preserve the signal instead of creating misleading digital patterns. Start with the signal’s bandwidth and range before choosing a filter, sample rate, or bit depth.

Follow one waveform across four beats to see how filtering, sample rate, and converter fit determine the digital evidence.

24.3 What the ADC Promises

An analog-to-digital converter, or ADC, is the snapshot gate between the physical world and the firmware record. A sensor produces a changing voltage. The ADC samples that voltage at scheduled moments and stores each result as a number.

The important idea is not "sample as fast as possible." The important idea is trust: a digital sample should still mean the physical thing it claims to mean.

Think of a flipbook. If you photograph a moving wheel often enough, the pages show the wheel turning in the correct direction. If you take too few photos, the same wheel can look slower, stopped, or even reversed. That false motion is aliasing. In ADC work, aliasing can turn high-frequency vibration, electrical noise, or switching ripple into a believable low-frequency pattern.

For example, an irrigation pump monitor might use a 0.5 V to 4.5 V pressure transducer on an STM32 or ESP32 SAR ADC. The dashboard may only need one pressure value each second, but the ADC path still needs to preserve pump ripple, cavitation pulses, and mains-coupled noise before the firmware decides what to summarize. A defensible design may sample around hundreds of samples per second, put an RC or active low-pass filter before the ADC input, and then report a one-second pressure statistic with a timestamp and scale factor. If the firmware sampled once per second directly, the data table would still fill with numbers, but a fast pressure pulse or electrical ripple could fold into a false slow drift.

The next What the ADC Promises decision depends on the diagram Figure 24.1. Reading ANALOG INPUT against 1. Sensor signal clarifies the practical meaning of ADC pipeline: signal conditioning, anti-alias filtering, sample timing, quantization, and a digital evidence record.

Read Figure 24.1 downward from continuous sensor voltage through the anti-alias filter. Sample and hold makes time discrete; the final converter stage makes amplitude discrete before firmware receives a code.

The One-Minute ADC Decision

Beginner Examples

• A greenhouse temperature sensor may only need one trustworthy reading every few seconds because the room changes slowly.
• A vibration monitor may need hundreds or thousands of readings per second because the useful fault pattern changes quickly.
• A higher-resolution ADC does not fix a wrong sample rate. More digits can still describe the wrong waveform.

Aliasing Warning Knowledge Check

If this gives you enough to recognize the risk, you can stop here. Continue to Practitioner when you need to design or review the sample path.

24.4 Apply It: Build the ADC Sample Plan

The practical ADC workflow starts with the signal requirement and ends with a short review record. The record matters because a sample rate that made sense in the lab can become wrong after a sensor, filter, enclosure, timer, or power rail changes.

Walkthrough: From Sensor Voltage to Digital Evidence

1. State the measurement. Name the physical quantity, expected range, fastest useful change, and acceptable delay.
2. Condition the voltage. Scale or shift the sensor output so it fits the ADC input range without clipping or wasting most codes.
3. Filter before sampling. Place the anti-alias boundary in the analog path. Digital filters cannot reliably remove content after it has folded into the sampled band.
4. Choose the sample rate. Start above twice the highest useful frequency, then add margin for filter rolloff, clock tolerance, jitter, and validation uncertainty.
5. Check resolution. Make sure one ADC code step is smaller than the meaningful physical change and larger than pure noise.
6. Validate and record. Use a known input, reference capture, or repeatable field test to prove the code record still maps to the physical signal.

An ADC selection guide keeps three reviews separate. Signal bandwidth drives the sample-rate and anti-alias plan; sensor accuracy and noise decide whether extra bits are useful; power budget constrains whether a faster or higher-resolution converter is practical for a battery device. Treat those as linked engineering choices instead of selecting the largest bit depth on the data sheet.

Read the three questions across the top of Figure 24.2 before looking at the converter recommendations below. Signal speed, sensor accuracy, and power budget constrain different parts of the choice.

Inspect the recommendations across the lower row of Figure 24.2, moving from coarse battery sensing toward precise, powered measurements. The upper questions explain these differences; extra converter bits are useful only when the sensor and noise level justify them.

Connect Walkthrough: From Sensor Voltage to Digital Evidence to the visual Figure 24.3 by locating Useful and signal band. The pair turns Nyquist decision map: useful bandwidth, filter cutoff, transition margin, and selected sample rate into something the team can verify.

Trace Figure 24.3 through Useful, signal band, and Filter. At the first stop, the diagram highlights Useful; at the second it highlights signal band; at the third it highlights Filter. Those hand-offs make Nyquist decision map: useful bandwidth, filter cutoff, transition margin, and selected sample rate actionable within Walkthrough: From Sensor Voltage to Digital Evidence.

Worked Example: Temperature Sensor on a 12-Bit ADC

Assume a temperature sensor produces 10 mV for each 1 degree C, and the conditioned output spans 0.1 V to 1.75 V. A 12-bit ADC using a 3.3 V reference has 4096 possible codes.

The calculation says the ADC has enough amplitude detail for many temperature tasks. It does not prove that the sample rate, reference stability, or calibration are good. Those are separate gates.

Try It: Sampling and Aliasing Visualizer

Use the ADC visualizer to move the signal frequency and sample rate. Watch the sample points thin out as the sample rate approaches the signal, then cross the Nyquist boundary to see the false lower-frequency pattern.

Incremental Practice

Sample-Rate Review Knowledge Check

If your job is to choose a defensible sample rate and record why it works, you can stop here. Continue to Under the Hood for the formulas behind the review.

24.5 Under the Hood: Math, Limits, and Failure Modes

The deeper layer explains why the practitioner workflow separates sampling, filtering, resolution, and evidence. Each gate answers a different physical question.

Sampling Boundary

The Nyquist rule gives the minimum sampling boundary for a highest useful frequency:

This boundary assumes the signal above the useful band has been removed before sampling. Real anti-alias filters have transition bands. A practical design usually samples faster than the bare minimum so the filter has room to attenuate unwanted content.

Alias Frequency

When a sinusoidal component at frequency f is sampled at f_s, a useful way to estimate the folded frequency is:

• A 90 Hz signal sampled at 100 samples/s aliases to 10 Hz.
• A 1200 Hz component sampled at 1000 samples/s aliases to 200 Hz.
• Two different high-frequency components can fold into the same apparent low-frequency band, which makes post-processing ambiguous.

Compare the real waveform on the left of Figure 24.4 with the reconstructed patterns beside it. The middle panel shows how insufficient sampling turns the original signal into a false lower-frequency pattern.

In Figure 24.4, sampling the 50 Hz signal at 80 Hz produces the false 30 Hz result in the middle panel. The right panel combines a higher sample rate with anti-alias filtering to preserve the original waveform.

Resolution and Quantization

For an ideal ADC with reference voltage V_ref and N bits:

The ideal quantization error is within plus or minus half an LSB. For a 12-bit, 3.3 V ADC, one LSB is about 0.806 mV, so the ideal quantization uncertainty is about +/-0.403 mV.

Ideal signal-to-quantization-noise ratio is often approximated as:

For 12 bits, that is about 74 dB. Real systems often deliver fewer effective bits because of input noise, reference drift, source impedance, aperture jitter, layout coupling, and calibration error. Effective number of bits can be estimated from a measured SNR:

24.6 Summary

• ADC design starts with the signal requirement, not the fastest available sample rate.
• Nyquist gives a lower boundary, while real designs need filter and implementation margin.
• Aliasing creates false patterns that can survive into dashboards and analytics.
• Anti-alias filtering must happen before sampling because digital cleanup cannot reliably undo folded content.
• Resolution depends on the whole signal path: range, noise, reference, timing, and calibration.
• A review record keeps the design reproducible when sensors, firmware, filters, or deployment conditions change.

24.7 See Also