34 SPI Protocol
34.1 Start With Speed and Selection
SPI trades extra wires for direct, fast transfers. A controller provides the clock, chooses one device with a select line, and shifts bits in both directions with little protocol overhead.
That makes SPI attractive for displays, radios, memory, and fast sensors, but the design still needs evidence: clock mode, maximum rate, chip-select timing, wiring length, and whether each peripheral can share the bus safely.
Overview: SPI Trades Wires For Deterministic Transfers
SPI is a short-distance synchronous serial bus for connecting a controller to board-level peripherals such as displays, ADCs, flash memory, radio modules, and sensors. The controller supplies the clock, selects exactly one peripheral with a chip-select line, and shifts data over MOSI and MISO at the same time.
The design trade is simple: SPI avoids addressing overhead and open-drain pull-up limits, but it spends pins. Shared SCLK, MOSI, and MISO lines can serve several peripherals, yet each independently selected peripheral usually needs its own CS line and its own timing contract.
That makes SPI attractive when the product needs predictable bursts of data rather than a self-describing network. A display controller can stream pixels, an external flash chip can clock blocks of bytes, and an ADC can return samples with tight timing because the controller owns the transaction cadence. The same explicitness is also the risk: if firmware asserts the wrong CS, uses the wrong clock phase, clocks too fast for the layout, or assumes a device releases MISO when it does not, there is no bus-level address scan or ACK layer to explain the mistake.
The overview decision is therefore a board-level fit decision. SPI is usually a good match inside one PCB, between stacked boards, or across a very short harness inside the same enclosure. It is weaker as a field cable or shared installation bus because signal integrity, grounding, connector stubs, and device-count wiring become the dominant constraints. For longer or noisier boundaries, a local SPI peripheral should normally sit behind a microcontroller, gateway, or transceiver that exposes CAN, RS-485, Ethernet, or a wireless interface to the outside world.
Synchronous
The controller clock defines when each bit is launched and sampled. Without the correct clock mode, the peripheral can read every bit on the wrong edge.
Full Duplex
Data shifts in both directions on the same clock stream. Some devices use only one direction, but the bus still clocks both paths.
Chip Select
CS is the transaction boundary. The selected peripheral drives or listens; the others should ignore the clocks and release the shared return line.
Selection rule: choose SPI when the peripheral needs predictable short-board transfers and the design can afford the pins, routing, and per-device chip-select discipline. Do not choose it only because it is faster on a datasheet; choose it when the board, firmware, and validation plan can preserve the timing margin that the speed requires.
Practitioner: Treat Each Peripheral As A Timing Contract
An SPI design is not complete when the four signal names are wired. Each peripheral datasheet defines clock mode, maximum clock rate, bit order, command framing, CS timing, bus idle behavior, and whether MISO is released when the device is not selected. Capture those terms before the board is routed and before firmware is written.
Use a per-device contract, not a single bus note. A microSD card, display controller, radio transceiver, and ADC can all share the same SPI controller while needing different clock rates, modes, setup times, and command sequences. The driver should configure those fields at the transaction boundary, and the schematic should make it obvious which GPIO owns each chip select. If an RTOS, DMA engine, or interrupt handler can start transfers from multiple tasks, add a bus lock and record who is allowed to change mode or speed.
Bring-up habit: validate one peripheral at a time at a conservative clock rate, capture SCLK/MOSI/MISO/CS on a logic analyzer, then raise speed only after mode, framing, and release behavior are proven. Keep one capture for a known-good register read and one for a failed or not-ready response, because those traces become the reference when the same driver later moves to the production board.
Under The Hood: The Bus Is Fast Because It Is Simple
SPI does not define a universal packet format, address field, arbitration scheme, acknowledgement, or error recovery method. That simplicity is why transfers can be efficient on a PCB, but it also means the application must define the safety rails: retries, status checks, CRC use when available, and what happens after a failed transaction.
Electrical details matter. The controller drives SCLK and MOSI, the selected peripheral drives MISO, and all devices share ground and compatible voltage levels. Long traces, weak return paths, too many stubs, or multiple peripherals driving MISO can create failures that look like firmware bugs.
The clock edge is the contract between digital logic and the physical route. CPOL defines the idle clock level; CPHA defines which edge captures the bit. At low speed with short wires, the wrong mode may still produce recognizable but shifted data. At higher speed, propagation delay, edge rate, ringing, crosstalk, and setup/hold margin decide whether a receiver samples the intended bit. That is why SPI speed should be validated on the final routing, not only on a development jumper.
Failure handling is also device-specific. Some flash memories expose status bits while an erase is in progress, some sensors require dummy clocks before valid data, some radios need an interrupt or ready pin before reading a FIFO, and some devices add CRC fields that firmware must actually check. Without those guards, a transfer can return bytes that are electrically valid but semantically stale, misaligned, or from the wrong command phase.
No Bus Arbitration
The controller owns the clock and selection. If two peripherals are selected together, the bus can produce invalid data or electrical contention on MISO. Firmware and board design must make simultaneous CS assertion observable and unlikely.
No Standard ACK
Many SPI transfers do not include an acknowledgement. Use device status registers, ready pins, CRC fields, or known-response reads when the device supports them, and log enough context to tell a protocol error from an electrical one.
Short Physical Reach
SPI is strongest inside one board or enclosure. For off-board wiring, reduce speed, control grounding, avoid long stubs, and consider a protocol or transceiver intended for cable runs.
Release rule: an SPI interface is ready when the timing mode, chip-select map, transaction framing, speed limit, electrical assumptions, ownership rules, and diagnostic readback are all recorded and tested on the target hardware. A useful release record includes the final SCLK rate, a logic-analyzer trace of a known register read, a MISO-release check with other peripherals deselected, and the fallback behavior when the expected status or CRC is not returned.
34.2 Summary
SPI is a controller-clocked serial bus for short, deterministic peripheral transfers. It uses SCLK, MOSI, MISO, and chip select to frame transactions without a standard address or acknowledgement layer. That simplicity is useful for displays, converters, memory, radios, and sensors, but it requires disciplined records: clock mode, chip-select ownership, transaction framing, speed, voltage, board layout, and readback checks.
34.3 Key Takeaway
SPI is fast because it is explicit. Record the timing mode, chip-select map, transaction format, electrical assumptions, and diagnostic readback before treating a peripheral as production-ready.
34.4 See Also
Wired Communication Fundamentals
Review clocking, duplex behavior, bus topology, and physical wiring constraints.
I2C Protocol
Compare SPI with the address-based two-wire bus used for many low-speed sensors.
UART and RS-232
Contrast SPI with point-to-point asynchronous serial links used for modules and debug ports.
Wired Access: Ethernet
Move from board-level serial links to networked wired access when distance and infrastructure matter.