8 PCB Design and Fabrication
Turn hardware measurements into board files, assembly notes, and bring-up tests
PCB design for IoT, hardware prototype PCB, schematic review, PCB layout validation, fabrication package, board bring-up
8.1 Start With the Story
Moving from breadboard to PCB feels like progress, but it can also freeze every untested assumption into copper. A stable sensor reading on loose wires does not prove footprint orientation, reset access, antenna keep-out, regulator heat, connector strain, or first-power bring-up. The PCB story should begin before layout with the question: what evidence says this circuit is ready to become a board?
Read the design steps as a risk filter. Schematic checks, footprint review, layout constraints, fabrication outputs, and bring-up notes all exist to make the first board teach the next revision instead of hiding the cause of failure.
Phoebe’s Why
A PCB trace is a resistor with a copper cross-section instead of a part number, and that resistance is what turns a “hot loop” from jargon into a measurable voltage. But copper does not conduct the same way at every frequency. At the low kilohertz rates a buck regulator switches at, current fills the whole copper thickness, so a simple bulk-resistance calculation is honest. At the hundreds of megahertz a LoRa radio transmits at, current crowds into a surface skin only a few micrometers deep, so the same copper behaves like a much thinner, higher-resistance conductor – which is exactly why this chapter treats “impedance notes” and “antenna keep-out” as separate concerns from ordinary power-trace sizing. Return current follows the same frequency split: at DC it takes the path of least resistance, but at radio and fast-switching frequencies it takes the path of least loop impedance, which hugs the plane directly under the signal trace. Slice that plane with a slot or a keep-out and the return current has to detour – the exact “hidden return-path break” this chapter’s own failure-pattern list warns about.
The Derivation
Trace resistance from copper’s bulk resistivity and cross-section:
\[R = \rho\,\frac{L}{w\,t}\]
Resistive (IR) voltage drop along that trace:
\[V_{drop} = I\,R\]
Skin depth sets how much of that cross-section actually carries current at frequency \(f\):
\[\delta = \sqrt{\frac{\rho}{\pi f \mu_0}}\]
Return-current routing is a loop-impedance problem, not a pure-resistance one:
\[Z = R + j\omega L\]
so once \(\omega L \gg R\), the return path collapses onto whatever route under the trace minimizes loop inductance – normally the copper directly beneath it, until a plane split forces a longer detour.
Worked Numbers: This Chapter’s Own Boards
- Trace resistance: a catalog-typical 50 mm, 20 mil (0.5 mm), 1 oz-copper (35 \(\mu\)m) run – a plausible buck-regulator-to-nRF52840 distance on the chapter’s field-node example – gives \(R=\rho L/(wt)=1.68\times10^{-8}\times0.05/(5\times10^{-4}\times3.5\times10^{-5})=0.0480\,\Omega\).
- IR drop at logic-level current: at a catalog-typical 120 mA combined nRF52840 + SX1262 TX-burst current, \(V_{drop}=0.120\times0.0480=5.76\) mV, only \(0.175\%\) of a 3.3 V rail – negligible, and consistent with the chapter treating signal traces as low-risk.
- IR drop at hot-loop current: at a catalog-typical 500 mA buck-inductor ripple peak, the same trace drops \(24.0\) mV, \(0.727\%\) of 3.3 V – over 4\(\times\) larger, which is the quantitative reason this chapter insists hot loops stay short and wide rather than “any resistance will do.”
- Skin depth at the buck’s switching rate (catalog-typical 500 kHz): \(\delta=92.3\,\mu\)m, larger than the 35 \(\mu\)m copper – the full cross-section still conducts, so the bulk-resistance math above is valid here.
- Skin depth at the radio’s 915 MHz: \(\delta=2.16\,\mu\)m, only \(1/16.2\) of the copper thickness – current is squeezed into a thin shell, so a simple DC resistance number badly understates RF trace loss. That is the physical reason antenna feed lines and RF keep-outs need controlled-impedance layout, not the same rule used for a power trace.
8.2 PCB Freezes Assumptions
Moving from breadboard to PCB is useful when the next risk is repeatability, enclosure fit, connector orientation, power integrity, signal return, service access, or assembly handoff. It is risky when the team uses layout to avoid unresolved schematic, footprint, or bring-up questions.
The board files should encode what the prototype already learned: power path, controller pins, sensor placement, connector pinout, reset and boot controls, programming access, test points, and the first-power sequence.
- Schematic readiness means the power tree, protection, reset, boot, buses, debug, and safe-state hardware are reviewable before routing.
- Layout readiness means power loops, return paths, antenna keep-outs, sensor placement, mounting, and service access are visible on the board.
- Bring-up readiness means the first article can be inspected, powered, programmed, measured, and stopped before damage spreads.
For example, a breadboarded room-monitoring node might use an ESP32-C3 module, an SHT31 temperature and humidity sensor, a status LED, a JST battery connector, and a USB-to-serial programming header. The breadboard can prove that the firmware reads the sensor and publishes MQTT messages. It does not prove that the SHT31 will be far enough from the regulator heat, that the battery connector polarity is visible to an assembler, that the boot pins have the right pulls, that the antenna keep-out remains clear inside the enclosure, or that the first board can be recovered if the firmware image fails. Those become PCB-stage questions.
A good board decision therefore starts by separating what is already known from what the board must teach. Known evidence might include the chosen sensor address, the tested pull-up value, the current draw during Wi-Fi association, the reset button behavior, and the debug header used during firmware work. Unknown evidence might include footprint orientation, connector strain, ground return under the radio module, regulator temperature, and whether a test point remains reachable after the lid is installed. If the unknowns are layout, assembly, service, and repeatability questions, a PCB is a useful next prototype. If the unknowns are still basic sensor choice, actuator current, or firmware state handling, the board risks freezing uncertainty into copper.
8.3 Check Manufacturing Package
For a prototype board, KiCad, Altium Designer, Eagle, EasyEDA, or another EDA tool is only the source. The handoff includes generated outputs that must agree with the revision being built.
- Electrical checks: run ERC, DRC, unconnected-net checks, net-class spacing checks, clearance rules, and intentional-exception review.
- Fabrication outputs: inspect Gerber or ODB++ layers, Excellon drill files, board outline, solder mask, silkscreen, paste layers, stackup notes, and impedance notes if used.
- Assembly outputs: check BOM manufacturer part numbers, alternates, do-not-populate parts, pick-and-place coordinates, polarity marks, pin-one marks, and special handling notes.
- Bring-up outputs: include rail names, expected voltages, current limits, programming tool, diagnostic firmware, pass criteria, stop conditions, and known rework options.
Use the generated package as the review target because manufacturers and assemblers do not build from the designer’s intent. Open the Gerbers in an independent viewer such as KiCad GerbView, a board-house previewer, or another CAM viewer. Check that the outline appears once, drills align with pads, copper pours connect where expected, solder mask openings are not missing, silkscreen does not cover pads, and top and bottom placement files are not mirrored incorrectly. Then compare the BOM against actual manufacturer part numbers, package variants, pin-one marks, and do-not-populate choices. A correct schematic symbol is not enough if the ordered switch, sensor, regulator, or JST connector is a different footprint variant.
The same discipline applies to first bring-up. Before applying power, inspect orientation marks, rail-to-ground resistance, solder bridges, connector polarity, and any parts that were intentionally left unloaded. Start with a current-limited bench supply or protected source, not a battery that can hide the first fault. Bring up the power section first where practical, then verify the controller rail, programming access, reset path, and a minimal diagnostic firmware image before loading the full application. A strong bring-up note names the board revision, loaded parts, current limit, expected rails, measured rails, programming tool, firmware build, fault symptoms, rework, and the next revision decision. That note is what turns a failed first board into useful design evidence.
8.4 Layout Quality Needs Current Loops
A schematic says nodes connect. The PCB decides how current returns, how noise couples, how heat leaves, and whether a human can debug the board. IoT boards often combine quiet sensors, radios, switching regulators, connectors, batteries, and human-service features in a small area.
- Power integrity: keep buck converter hot loops short, place decoupling capacitors close to pins, size copper for load current, and expose rail test points.
- Signal integrity: preserve ground return near I2C, SPI, UART, clocks, interrupts, PWM, ADC references, and radio-module control lines.
- RF and sensors: respect antenna keep-outs, ground clearance, sensor exposure, thermal isolation, ESD paths, and enclosure materials that change readings.
- Safety and service: check creepage, clearance, fuse or polyfuse placement, TVS placement, keyed connectors, reset access, SWD/JTAG/UART access, and current-measurement jumpers.
The first board is successful when it teaches the next revision quickly, not merely when it arrives from the fabricator.
The loop view explains why two layouts with the same schematic can behave differently. A buck regulator’s high-current switching loop should be short, with the input capacitor, switch, diode or synchronous path, inductor, and ground return placed so current does not travel across the sensor area. A microcontroller power pin needs a nearby decoupling capacitor with a short return to ground; placing the capacitor on the far side of a connector or routing its ground through a narrow detour can make reset and radio transmit faults more likely. An ADC input for a thermistor, current shunt, or battery divider needs a quiet reference path and often filtering near the measurement point, not beside a motor driver or relay coil.
Radio and enclosure decisions add another layer. ESP32, nRF52, LoRa, LTE-M, NB-IoT, Thread, and Wi-Fi modules often specify antenna keep-outs, ground clearance, placement at a board edge, and restrictions on copper or metal near the antenna. A board can pass DRC while still burying the antenna under a battery, enclosure post, cable, or ground pour. Sensor boards have similar physical constraints: a temperature sensor placed near a regulator may measure board heat, a humidity sensor under conformal coating may respond slowly, and a microphone or pressure sensor may need a real opening. Layout review is therefore part electrical review and part physical evidence review.
Service access is also a circuit decision. SWD, JTAG, UART, reset, boot, current-measurement links, and rail test points should remain usable after partial assembly and enclosure fit checks. If a test point disappears under a module or a programming header requires removing the battery, bring-up slows down and faults become less reproducible. The under-the-hood goal is to preserve the evidence path: current flows can return cleanly, signals can be measured, firmware can be recovered, and the next revision can be based on observed behavior instead of guesswork.
8.5 Learning Objectives
By the end of this chapter, you will be able to:
- Decide when breadboard evidence is strong enough to move into a custom PCB stage.
- Review a schematic and footprint set before layout begins.
- Place and route components using power, return-path, connector, sensor, and radio constraints.
- Prepare a fabrication and assembly package that another builder can inspect.
- Bring up a new board safely and record revision evidence for the next design turn.
8.6 From Prototype to PCB
A custom board removes jumper-wire uncertainty, but it introduces layout, footprint, assembly, and bring-up uncertainty. The design should move to a PCB when the current prototype needs stronger evidence about repeatability, packaging, service access, power integrity, signal behavior, or assembly handoff.
The PCB stage should answer questions such as:
A working breadboard is useful evidence, but it does not prove footprints, trace routing, ground return, connector orientation, assembly sequence, or enclosure behavior. Treat PCB layout as a new evidence gate.
8.7 Schematic and Footprint Readiness
The schematic should describe more than logical connectivity. It should also include power entry, protection, pull resistors, decoupling, programming or update access, reset behavior, indicators, test points, and any safe-state hardware.
Before layout, review these items:
Print or view the layout at actual size before ordering boards. Compare connectors, modules, switches, headers, and polarized parts against the physical parts or trusted package drawings.
8.8 Layout Planning
Good layout starts with zones. Connectors, power entry, radio or antenna areas, sensors, high-current loads, quiet analog circuits, and debug access should not compete for the same space.
Use placement to make the important paths short and inspectable:
8.9 Power, Ground, and Return Paths
Most first-board failures are not caused by the schematic being completely wrong. They come from missing decoupling, interrupted return paths, weak power distribution, reversed connectors, inaccessible test points, or a bring-up sequence that hides the first fault.
During layout review, check:
8.9.1 Layer Count Decision
Layer count is an engineering tradeoff, not a badge. A simple low-speed board can often start with two layers if ground return remains continuous and routing is not forced into long detours. Move to more layers when routing density, controlled impedance, split power domains, quiet analog return, radio layout, or high-speed interfaces make the two-layer return path fragile.
Do not ask, “Can the router finish?” Ask, “Can the return paths, power paths, test points, and keep-outs still be inspected after routing?”
8.10 Fabrication and Assembly Package
The fabrication package is the handoff from design intent to board production. It should be complete enough for someone else to inspect, fabricate, assemble, and bring up the board without guessing which file is authoritative.
Prepare and review:
Passing a design rule check is not enough. Inspect the generated outputs directly. Many errors come from wrong layer export, missing drill files, mirrored placement, hidden outline problems, or footprints that passed rules but do not match the part.
8.11 First Article Bring-Up
The first assembled board should be brought up in small steps. The goal is to localize faults before they damage parts or bury the evidence under full firmware behavior.
Treat soldering as part of bring-up, not as a separate craft step. Before heating the board, lay out the parts, values, orientation marks, jumpers, wire links, and expected no-connects against the schematic. Prepare the iron with a clean, tinned tip, use enough heat to wet the pad and lead quickly, and keep cleaning and re-tinning the tip as flux and oxide build up. After each small group of joints, inspect for bridges, cold joints, lifted pads, reversed parts, and clipped-lead debris before adding the next group.
For a small amplifier board, compare the PCB against the breadboard before trusting the result. Start with continuity and rail checks, then power the board through current limiting, confirm the op-amp supply pins, and drive a known input. An LED or other simple indicator can show whether the output crosses the expected threshold, but it should be read as a test result, not as proof of the whole analog design. If the breadboard passes and the PCB fails, isolate the difference: feedback resistor values, input polarity, op-amp channel pins, supply reference, solder bridges, and whether the output load changes the amplifier behavior.
Use a ladder like this:
8.11.1 Example Bring-Up Record
board=room-node-rev-a
stage=first-article-bring-up
loaded_parts=power entry, regulator, controller, programming header, status indicator
pre_power=rail-to-ground resistance checked, connector orientation checked, visual inspection passed
power_limited_test=main rail stable, current within expected no-load range
programming=minimal diagnostic firmware loads and reset works
faults=sensor connector pin order ambiguous, one test point hidden after enclosure fit
decision=revise connector symbol, move test point, continue subsystem testing on current board
next_revision=rev-b schematic and layout notes opened8.12 Incremental Examples
8.12.1 Breakout-to-Carrier Board
A breadboarded ESP32-C3 sensor node uses a known SHT31 module, a JST battery connector, a programming header, and one status LED. The first PCB should be a carrier board that reduces wiring risk without pretending the design is production-ready.
- Copy the proven pinout into a schematic with explicit rail names, pull-ups, reset access, boot strap behavior, and test points.
- Verify the JST connector, module header, LED polarity, programming header, mounting holes, and enclosure clearance against physical parts or trusted package drawings.
- Bring up the board with current limiting, then check the 3.3 V rail, programming access, I2C scan, LED output, and sleep-current path before loading full firmware.
This is a beginner case because the board mostly preserves a known module-based prototype. The main evidence is whether the PCB removes wiring ambiguity while keeping debug access visible.
8.12.2 Custom Sensor and Power Section
A field node moves from modules to a board with an nRF52840, a BME280, a load switch, a LiPo charger, a buck regulator, and a current-measurement jumper. The PCB now owns more electrical behavior.
- Review regulator input range, charger protection, battery connector polarity, buck converter hot loop, decoupling capacitor placement, and BME280 exposure away from heat sources.
- Inspect generated Gerbers, Excellon drills, solder mask, paste layer, board outline, BOM, and pick-and-place file in an independent viewer.
- Assemble power and programming sections first, then add the sensor and radio path only after rail current, reset behavior, and SWD access are proven.
This case is harder because footprint and layout decisions can change the measurement. A correct schematic is not enough if the sensor is heated by the regulator or the debug pads disappear under the enclosure.
8.12.3 Portable Condition Monitor PCB
A team has a functional prototype that samples vibration and temperature, logs local events, and reports summaries through a nearby gateway. The breadboard proved the sensing concept, but the team needs a board that can fit in an enclosure, survive cable strain, and support repeatable field tests.
8.12.4 PCB Review Plan
8.12.5 Review Decision
decision=proceed-to-board-revision
why=breadboard answered sensing question, but enclosure fit and repeatable wiring remain unproven
layout_focus=power entry, sensor isolation, connector strain, programming access, test points
assembly_focus=load power section first, then controller, then sensor and output sections
stop_condition=unexpected rail current, unstable reset, missing programming access, or overheated part8.13 Try It Now
Choose one breadboarded hardware prototype and write a PCB gate note with three parts: the evidence that is strong enough to freeze into copper, the evidence that still needs a layout or footprint check, and the first measurement that would stop first-power bring-up.
8.14 Spot Fabrication Risk Early
A team exports Gerbers for a battery node with an SHT31 sensor, SX1262 LoRa module, buck regulator, SWD pads, and JST battery connector. The DRC passes. The board outline fits the enclosure.
Name two checks still required before ordering. Strong answers include connector polarity, pin-one marks, antenna keep-out, sensor airflow, regulator hot-loop area, decoupling placement, drill alignment, paste layer, BOM manufacturer part number, pick-and-place rotation, test-point reach, and whether the SWD pads remain accessible inside the enclosure.
8.15 Concept Check: PCB Stage Gate
8.16 First Power Stop Condition
8.17 Match PCB Evidence to the Review Gate
8.18 Order the First-Board Bring-Up
8.19 Common Failure Patterns
The schematic is correct, but the physical part does not match the footprint, pin numbering, pad size, courtyard, or orientation mark. Review packages against physical parts or trusted package drawings before ordering boards.
The board routes successfully, but ground return is sliced by traces, slots, keep-outs, or layer changes. The result may be noisy sensing, reset instability, or unreliable communication.
Programming pins, reset, test points, buttons, or current-measurement links are reachable on the bench but blocked by the enclosure, cables, or mounted components.
Every part is assembled before rails are checked. A simple power-path error then becomes harder to diagnose and may damage parts that did not need to be loaded yet.
8.20 Summary
PCB design is a controlled evidence gate between a flexible prototype and a repeatable hardware build. Review schematic completeness, footprint reality, layout constraints, output files, assembly order, and bring-up results as separate decisions. A clean PCB review leaves enough evidence for another builder to fabricate, assemble, test, and revise the board.
8.21 Key Takeaway
PCB design should begin only after interfaces, power paths, connectors, debug access, firmware assumptions, and bring-up tests are stable enough to review.
8.22 See Also
- Hardware Platforms - compare platform roles after board-level constraints are understood.
- Hardware Components - connect component choices to footprints, power paths, and test evidence.
- Best Practices and Debugging - use systematic debugging records during board bring-up.
- Case Studies and Worked Examples - review how evidence records guide hardware revisions.