20 Logic Level and Level Shifting Contracts

20.4 Overview: Four Numbers Define a Logic Interface

Two chips talk digitally only if they agree on what voltages mean 0 and 1. Every logic interface is governed by four numbers: what a driver outputs and what a receiver requires.

When two devices use different supply rails, a shared word such as HIGH is not yet an electrical contract. Inspect Figure 20.1 to identify the two voltage domains and the translator boundary before checking the four guaranteed output and input levels.

The left side of Figure 20.1 is the 3.3V DOMAIN, powered through VCCA and connected on channels A1–A3; the right is the 5V DOMAIN, powered through VCCB and exposed on B1–B3. The central TXS0108E marks the translation boundary, while ↔ AUTO DIR shows that signals may travel either way. That topology does not by itself prove compatibility: the stated voltage range and speed are device capabilities, and the interface review must still compare $V_{OH}$ with $V_{IH}$, $V_{OL}$ with $V_{IL}$, direction behaviour, and absolute-maximum limits for the chosen bus.

A valid HIGH link needs the driver's VOH to clear the receiver's VIH; whatever is left over is the noise margin that keeps interference from being misread — the same margin that gives digital signals their noise immunity.

Worked example: an ESP32 output is powered from 3.3 V and its HIGH output is close to 3.3 V when lightly loaded. A 5 V TTL input may require only VIH = 2.0 V. The HIGH noise margin is therefore about 3.3 - 2.0 = 1.3 V. A cable transient or ground offset would have to steal more than 1.3 V before the receiver stops seeing a HIGH, so this direction is usually safe from a logic-threshold point of view.

The opposite direction is a different risk. A 5 V output connected directly to a 3.3 V microcontroller input may be read as HIGH, but it can exceed the input's absolute maximum rating. A correct review separates "will the bit be interpreted correctly?" from "will the pin survive?" That is why a circuit note should list both threshold margin and absolute-maximum protection, not just a casual statement that the voltages are close enough.

For beginner IoT boards, the practical checklist is simple: identify the driver supply, receiver supply, guaranteed output levels, required input thresholds, and pin maximum voltage. If any number is missing, do not assume compatibility. Look up the datasheet, add a level shifter, or constrain the interface to an open-drain bus with the correct pull-up rails.

20.5 Check a Five-Volt Reply Before Connection

For this logic-level contract, a 3.3 V controller sends a clock to a 5 V sensor board and expects data back on another wire. A logic HIGH is not a universal voltage: the sender’s guaranteed output must cross the receiver’s input threshold without crossing its absolute limit. Figure 20.1 places VCCA and A1–A3 in the 3.3 V domain, VCCB and B1–B3 in the 5 V domain, and the translator between them. At the level-shifting boundary, read each rail before following a signal arrow.

In the digital link, an illustrative 5 V receiver with (V_{IH}=0.70\times V_{CC}) recognises HIGH from (0.70\times5=3.50\ \text{V}). For this logic-level contract, a 3.3 V output cannot meet that stated threshold, so a direct controller-to-sensor HIGH has negative margin. At the return level-shifting boundary, a 5 V output can exceed a non-tolerant 3.3 V input even though the bit value is correct.

An open-drain bidirectional bus needs a different check. With a 4.7 kΩ pull-up and an illustrative 50 Ω low-side resistance, the low node is (5\times50/(4700+50)=0.0526\ \text{V}), or 52.6 mV. That is safely near zero for many inputs, but pull-up value, bus capacitance, rise time, and the specific translator still decide whether the edge arrives on time.

20.6 Practitioner: Shifting Down Is Easy, Shifting Up Is Not

The two directions are not symmetric. Going down (5 V → 3.3 V) mainly protects the lower-voltage input, whose absolute maximum is only a little above its own supply. For a slow, unidirectional push-pull signal a resistor divider is enough:

Vout = Vin × R2 / (R1 + R2). Put R1 = 1 kΩ in series from the 5 V signal and R2 = 2 kΩ to ground: Vout = 5 × 2 / (1 + 2) = 3.33 V — a safe HIGH for the 3.3 V input.

Going up (3.3 V → 5 V) is different. If the 5 V receiver is CMOS it needs VIH ≈ 0.7 × 5 = 3.5 V, and a 3.3 V output falls just short. A resistor divider cannot help — dividers only attenuate, never add voltage. You need something active: a MOSFET or transistor level-shifter, a dedicated level-translator IC, or an open-drain line with its pull-up tied to 5 V so the HIGH is pulled up to the higher rail.

Do not choose divider values by ratio alone. The divider above has total resistance 3 kΩ, so it draws 5 V / 3 kΩ = 1.67 mA whenever the input is HIGH. That is acceptable on a bench, but wasteful for a sleeping battery node. Scaling to 10 kΩ and 20 kΩ keeps the same 3.33 V output while reducing divider current to 0.167 mA. The tradeoff is edge speed: with 20 pF of input plus wiring capacitance, the Thevenin resistance is about 6.7 kΩ, giving an RC time constant near 134 ns. That is fine for a slow enable pin, but not a reason to use dividers casually on fast buses.

A practitioner review should also name the signal direction. A unidirectional "5 V interrupt output into ESP32 GPIO" can use a divider or translator. A bidirectional "3.3 V MCU and 5 V sensor share I2C" cannot be reviewed as two independent one-way signals, because either side may pull the line low. In that case, choose a bidirectional MOSFET shifter or a translator IC and size pull-ups for the bus speed and capacitance.

20.7 Under the Hood: Bidirectional Buses and Absolute Maximums

A resistor divider is not just up-shift-incapable — it is also unidirectional and speed-limited (its resistance and the line capacitance form an RC that softens fast edges). That fails a shared bus like I2C, where both sides must be able to drive the line. The standard trick is to make the lines open-drain with a pull-up on each side and place a single N-channel MOSFET per line (the classic BSS138 bidirectional shifter): when either side pulls low, the MOSFET couples the low across, and when released each side floats up to its own rail. That is why bus level-shifting looks different from a simple signal divider.

The reason down-shifting is mandatory, not optional, is the absolute-maximum input rating: a 3.3 V pin usually tolerates only about Vcc + 0.3 to 0.5 V before its internal clamp diodes conduct hard and it risks damage or back-powering its own rail. So drive a lower-voltage input from a higher-voltage source only through a proper shift — never by trusting the clamp diodes to survive a continuous overvoltage.

The MOSFET bus shifter works because the body diode and gate bias make a low level propagate across domains while released lines rise independently. On a 3.3 V / 5 V I2C link, the low side is pulled up to 3.3 V and the high side to 5 V. If the 3.3 V device pulls SDA low, the MOSFET conducts and drags the 5 V side low too. If the 5 V device pulls low, the body diode first nudges the low side down, then the MOSFET turns on and completes the low-level transfer. When neither device pulls, each side returns to its own safe HIGH.

Pull-up sizing is part of the evidence. With 4.7 kΩ pull-ups to 3.3 V, each LOW sinks about 3.3 V / 4.7 kΩ = 0.70 mA on that side. Stronger pull-ups such as 2.2 kΩ sharpen edges but increase sink current; weaker pull-ups reduce current but may fail rise-time limits on long wires. If a sensor board works at 100 kHz on a short jumper but fails at 400 kHz after the harness is installed, the level shifter may be electrically correct while the RC rise time is still too slow.

A final under-the-hood trap is back-powering. If a powered 5 V module drives a line into an unpowered 3.3 V microcontroller through its protection diode, the microcontroller rail can rise partially even though its regulator is off. That can create ghost boot states and latch-up risk. A robust design avoids continuous clamp current, sequences rails deliberately, or uses a translator with power-off isolation.