26 ADC Fundamentals: Architectures and Interfaces

26.1 Start With the Situation

The required resolution is known, but a bit count does not choose the converter. The team must compare architecture, speed, power, reference stability, source impedance, and noise before the sensor reading can be trusted.

26.2 Overview

This route compares ADC architectures and carries the choice into interface, noise, reference, and deployment evidence.

This is part 2 of 2. Review ADC Fundamentals: Conversion and Resolution when you need the first route.

26.3 Learning Objectives

By the end of this chapter, you will be able to:

• compare SAR, sigma-delta, and flash ADC architectures
• select an ADC from resolution, speed, and power requirements
• control reference, noise, and interface errors in a sensor chain

26.4 Chapter Roadmap

Follow the original sections below in order. They begin at the reviewed split boundary and keep every worked example, figure, check, and supporting banner with the section that owns it.

26.5 ADC Architectures

Once the voltage step is clear, the next question is how the converter finds that code. The architecture determines whether the design prioritizes microsecond conversion, high resolution, low current, or simple integration.

Real-world ADCs use different conversion techniques optimized for speed, accuracy, and power consumption. The most common architecture in IoT microcontrollers is the Successive Approximation Register (SAR) ADC. In Figure 26.1, identify the proposal-and-comparison loop before reading the numbered bit decisions.

Follow the loop in Figure 26.1 rather than reading the blocks as a one-way chain. The sample-and-hold keeps the unknown input steady. SAR logic proposes a code, the internal DAC turns that proposal into a comparison voltage, and the comparator reports whether the proposal is above or below the held input. The logic keeps or clears one bit and repeats with a finer proposal. That feedback loop is the physical meaning of the “binary search” described next.

How SAR ADC Works (Binary Search):

The SAR ADC determines the digital output by testing each bit sequentially, starting from the Most Significant Bit (MSB) down to the Least Significant Bit (LSB):

1. Initial State: All bits set to 0, test voltage (V_test) = 0V
2. Test MSB (bit 11 for 12-bit ADC): Set bit to 1, DAC outputs V_test = Vref/2
   • If V_input > V_test: Keep bit = 1 (input is in upper half)
   • If V_input < V_test: Clear bit = 0 (input is in lower half)
3. Test bit 10: Adjust next bit, DAC outputs new V_test
   • Repeat comparison and decision
4. Continue for all 12 bits (bit 11 → bit 0)
5. Result: 12-bit digital value represents input voltage

Example: Converting 2.0V with 12-bit SAR ADC (Vref = 3.3V)

SAR ADC Advantages for IoT:

• Fast Conversion: Typically 1-12 us per sample depending on configuration (ESP32: ~12 us default, faster with DMA)
• Low Power: ADC peripheral draws only a few mA during conversion
• Moderate Complexity: Simpler than pipeline ADCs, faster than integrating ADCs
• Widely Used: Arduino Uno (10-bit SAR), ESP32 (12-bit SAR), STM32 (12-bit SAR)

SAR is a balanced choice, not a universal winner. A flash ADC makes many comparisons in parallel, trading circuit area and power for very low conversion latency. A pipeline ADC divides a conversion across stages so that new samples can enter before earlier ones leave, which suits sustained high-throughput acquisition. A sigma-delta ADC uses oversampling, feedback, and digital filtering to favour fine low-bandwidth measurements over immediate results. These are architectural tendencies; the data sheet still decides whether a particular device meets the required bandwidth, noise, latency, and energy budget.

the linked figure in Part 1-architecture-tradeoffs places those tendencies on two axes before you choose a part. Read horizontal position as relative conversion speed and vertical position as relative resolution, then use the colour-coded power note as a third constraint. The positions are comparative, not a substitute for measured specifications.

In the linked figure in Part 1-architecture-tradeoffs, start with SAR near the middle: it is often the sensible built-in converter when no single extreme dominates. Move toward flash or pipeline when the signal requires much more throughput and the system can accept the implementation cost. Move toward sigma-delta when the signal changes slowly enough that filtering and conversion latency are acceptable in exchange for lower in-band noise and finer effective resolution. This comparison connects the internal conversion method to the system-level choice: select an architecture only after defining how fast the signal changes and how small a trustworthy change must be.

26.6 Analog-Digital Interface Challenges

Architecture is only part of measurement quality. The front end still has to protect the ADC from noise, source impedance, reference drift, and out-of-band signal content.

Converting real-world analogue signals to digital values introduces several practical challenges. the linked figure in Part 1-noise-sources groups the uncertainty sources around the conversion path so that each later remedy can be tied to the place where its error enters.

Read the linked figure in Part 1-noise-sources from the sensor toward the code. Disturbance can enter with the signal, through the power and reference rails, through the circuit’s resistive elements, or through uncertain sampling time. Quantization then adds a different limitation: even a perfectly clean held voltage must be assigned to one available code. Because these mechanisms enter at different points, “use more bits” cannot be the universal remedy. The diagnostic order is to identify where uncertainty enters, limit it there, and only then ask whether ADC resolution is the remaining constraint.

Key Interface Challenges

1. Quantization Noise (Inherent ADC Limitation)

Quantization error is the difference between the input and the representative level selected for its code. For an ideal converter that rounds to the nearest level, its magnitude is bounded by roughly half a step: $V_{ref}/2^{n+1}$ for a unipolar span from zero to $V_{ref}$. A higher-resolution converter makes that ideal step smaller. Oversampling and averaging can reveal finer information when suitable noise moves the signal across code boundaries, but they do not correct reference error, clipping, or systematic nonlinearity.

2. 1/f Noise (Flicker Noise)

Flicker noise rises toward lower frequencies in many semiconductor devices, so it matters especially when measuring DC and slowly changing signals such as temperature or pressure. Simply collecting more readings may not help as much as it would for independent white noise because successive errors can be correlated. Chopper-stabilised front ends, modulation techniques, careful component choice, and a bandwidth appropriate to the signal are possible controls; the correct choice depends on whether the wanted measurement includes DC.

3. Thermal Noise (Johnson-Nyquist Noise)

Thermal noise is random voltage noise associated with resistance and temperature. Its RMS value over bandwidth $Δf$ is described by $V_{rms}=\sqrt{4kTR\Delta f}$. The relationship gives two practical levers: avoid unnecessarily large resistance in noise-critical nodes and do not admit bandwidth the signal does not need. Averaging can reduce the contribution when samples are sufficiently independent, but it trades response time for lower random uncertainty.

4. Power Supply Noise

Switching regulators, radios, clocks, and actuators can couple disturbance into the input, ground return, supply, or reference. Treat the reference as part of the measurement, not merely as a power pin: movement in the reference changes the meaning of every code. Keep high-current switching paths away from sensitive analogue paths, place the manufacturer-recommended decoupling close to the relevant pins, and follow the converter data sheet’s grounding and layout guidance. A blanket split-ground rule can create a worse return path, so verify current flow on the actual board.

Best Practices for Clean ADC Readings:

The common thread is to match every remedy to a mechanism. Use an anti-alias or low-pass filter when unwanted bandwidth is entering the sample; average only when the error behaves like reducible random noise; choose and decouple the reference according to the accuracy budget; control return-current paths in the layout; and calibrate offset or gain when the product has a trustworthy reference condition. After those controls, repeated readings and known inputs can show whether the remaining uncertainty comes from the sensor, front end, reference, or converter.

26.7 ADC Resolution Comparison Table

26.8 Typical Microcontroller ADCs

LSB = Least Significant Bit (smallest measurable change)

void setup() {
  Serial.begin(9600);
}

void loop() {
  // Read analog sensor on pin A0
  int sensorValue = analogRead(A0);  // Returns 0-1023

  // Convert to voltage (10-bit ADC, 5V reference)
  float voltage = sensorValue * (5.0 / 1024.0);

  // Convert to temperature (TMP36 sensor: 500mV offset, 10mV/C)
  float temperatureC = (voltage - 0.5) * 100;

  Serial.print("Sensor: ");
  Serial.print(sensorValue);
  Serial.print(" | Voltage: ");
  Serial.print(voltage);
  Serial.print("V | Temp: ");
  Serial.print(temperatureC);
  Serial.println("C");

  delay(1000);  // Read every second
}

26.8.2 Complete ADC Workflow Visualization

The code example above begins at analogRead(), but a trustworthy measurement begins earlier and continues later. Use the linked figure in Part 1-signal-path to locate the ADC inside the complete information path. Read from the physical quantity at the top toward network transmission at the bottom, and notice which stages can still change measurement quality.

The first three stages in the linked figure in Part 1-signal-path form the analogue-to-digital measurement boundary. The sensor turns the physical quantity into an electrical signal, signal conditioning scales and filters it, and the ADC samples and quantizes it. Everything below that boundary operates on the resulting code: processing may calibrate or convert units, formatting gives the reading a data representation, and packet and network stages move it elsewhere. If a reading is already clipped, noisy, or too coarsely quantized at the ADC stage, the downstream stages can label the problem but cannot reconstruct the missing measurement. That is why ADC selection belongs in an end-to-end sensor workflow rather than as an isolated bit-depth choice.

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ADC Resolution Misconceptions

The Myth: Many IoT developers believe that using a 16-bit ADC instead of a 12-bit ADC automatically improves measurement accuracy.

The Reality: Sensor accuracy, not ADC resolution, is the limiting factor in 83% of IoT applications.

Real-World Example - Soil Moisture Monitoring:

A 2019 agricultural IoT study found that upgrading from 12-bit to 16-bit ADCs provided zero measurable improvement in 83% of installations because:

• Capacitive soil moisture sensors: +/-2% accuracy (66mV error at 3.3V)
  • 12-bit ESP32: 0.806mV resolution (82x finer than sensor accuracy)
  • 16-bit ADS1115: 0.0504mV resolution (1,310x finer than sensor accuracy)
  • Result: Both ADCs capture the same sensor limitations

When 16-bit ADC Actually Matters (the 17% where it helps):

• Thermocouples: Type K generates 41uV/C → 16-24 bit ADC essential for 0.1C resolution
• Load cells (precision weighing): 0.01% accuracy requires uV-level precision
• Medical ECG: 1mV signals need high resolution to detect subtle arrhythmias
• pH sensors: 59mV/pH unit → 16-bit ADC needed for 0.01 pH resolution

Best Practice: Match ADC resolution to sensor accuracy - don’t waste money on 16-bit ADCs for +/-2-5% accuracy sensors!

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Knowledge Check: ADC Resolution

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26.9 Real-World IoT ADC Applications

Understanding ADC requirements helps you select the right hardware for an IoT project, but application names alone do not select a converter. the linked figure in Part 1-iot-requirements is a circuit-level reminder of the decision inputs. Trace the sensor voltage into the ADC, locate the reference that defines the code scale, and then follow the digital output into the processor. Each connection corresponds to a question the application table must answer.

In the linked figure in Part 1-iot-requirements, the input connection prompts questions about the sensor’s voltage span, source impedance, useful bandwidth, and required smallest trustworthy change. The reference connection prompts questions about how stable and accurate the scale must be. The digital side prompts questions about how quickly results are needed and how the processor will read them. The rows below summarise common starting points, but the surrounding signal and timing requirements—not the category label—justify the final part choice.

The opening light-sensor example is a useful concrete case. Before looking at the photograph, connect it to the first row: the sensing element does not emit a digital light value. It changes resistance, so a divider or other front end must first turn that change into a voltage within the ADC’s input range.

Follow the component from its orange sensing track to its two leads. Light changes the track’s resistance; the surrounding circuit converts that resistance into a voltage; the built-in ADC assigns the voltage a code. The photograph therefore reconnects the application table to the chapter’s running pipeline: a “basic monitoring” sensor is simple only after its analogue behaviour, conditioning circuit, reference, and required resolution have been checked.

The precision logger example below uses the same workflow in a tighter setting: start from the sensor’s voltage per degree, compare that to ADC step size, then decide whether the built-in ADC is enough.

26.10 ADC Architecture Contracts

The main chapter above stays focused on ADC operation, resolution formulas, quantization, architectures, and selection workflow. For the deeper design contract behind SAR input settling, sigma-delta oversampling, dither requirements, and noise shaping, continue to ADC Architecture and Resolution Contracts.

26.11 Summary

This chapter covered Analog-to-Digital Converters (ADCs) - the essential bridge between analog sensors and digital microcontrollers.

26.11.2 Decision Framework

Use the linked figure in Part 1-decision-tree as a route through the chapter’s decisions, not as a bit-depth lookup. Start at signal bandwidth, then follow the branches through sensor accuracy and power budget. At every branch, carry forward the input range, reference quality, and noise evidence established earlier.

Read the linked figure in Part 1-decision-tree from the first question rather than jumping to a recommendation. Bandwidth constrains how quickly the converter and front end must respond. Sensor accuracy then prevents buying code resolution that the source cannot support, while the power branch tests whether the technically capable option fits the device’s energy budget. The destination boxes are starting classes for investigation; a real selection still requires data-sheet limits and measurements. This brings the running narrative together: architecture, reference, resolution, sampling, and noise form one evidence-backed choice.

Knowledge Check: Putting It All Together

26.12 What’s Next?

Now that you understand ADC fundamentals, you have a critical question to answer: How fast should you sample? the linked figure in Part 1-complete marks that hand-off. Read it from the completed conversion concepts on the left toward sampling theory on the right; the arrow is a dependency, not just a next-page link.

The completed side of the linked figure in Part 1-complete gives you the converter vocabulary: sample, quantize, encode, and evaluate noise. The next side asks how closely sample times must be spaced so that changing signal content is represented rather than misidentified. Nyquist-Shannon sampling theory supplies that constraint, and the following chapter connects it to anti-alias filtering and practical sample-rate choice.

Continue to Nyquist Sampling Theory →