27 ADC Architecture and Resolution

electronics-controller-design

adc

analog-digital

signal-conditioning

27.1 Start Simple

Choose the Converter From the Signal’s Job

Picture a fast motor-current pulse and a slow strain reading. Two converters can advertise the same number of bits yet miss different parts of those signals. The first choice starts with what must be detected and by when.

An analog-to-digital converter is a circuit that turns a measured voltage into a number; ADC is its short name. Bandwidth means the range of signal changes the measurement path must carry. Latency means the time from an input change to the result that matters.

Apply a known step and a known changing signal. Record source resistance, settle time, sample time, noise, output rate, delay, and useful code spread. Change source resistance, speed up the input, repeat, and restart. Reject a bit count that the full path cannot support.

This runway does not prove that one converter design is best for every sensor. The deeper sections compare successive-approximation and noise-shaped converters, settling, oversampling, filtering, resolution, delay, and usable accuracy.

Imagine two ADCs with the same number of bits but different internal behavior. A SAR ADC may need a low-impedance source that settles quickly, while a sigma-delta ADC trades speed for noise performance through oversampling. Start with the signal bandwidth, source impedance, noise target, and conversion time before choosing an architecture.

27.2 Learning Objectives

After this page, you should be able to:

Choose SAR or sigma-delta ADCs based on speed, resolution, latency, and IoT signal bandwidth.
Calculate least significant bit size and separate converter resolution from usable measurement accuracy.
Check SAR source impedance, sample-capacitor settling, and acquisition-time constraints before trusting readings.
Use oversampling only when throughput and dither/noise conditions can support extra effective bits.
Explain how sigma-delta noise shaping and decimation turn fast low-resolution samples into slow high-resolution readings.

27.3 Why This Follows How ADCs Work

How ADCs Work builds the main conversion model: sample an analog voltage, quantize it against a reference, encode a digital code, and match converter resolution to sensor needs. This page tightens that model into design contracts for real hardware.

Use it when a product decision depends on SAR versus sigma-delta architecture, a resistor divider or weak sensor may not drive the ADC input quickly enough, or a data sheet promises more bits than the sensor, reference, and sample budget can actually deliver.

Phoebe’s Field Notes: Where +9 dB and +15 dB Per Octave Come From

The mathematical gist. An order- $L$ noise shaper makes in-band quantisation-noise power fall as $1/OSR^{2L+1}$ . Doubling OSR therefore gains $(2L+1)3.01$ dB: 3.01 dB for plain oversampling, 9.03 dB at first order, and 15.05 dB at second order. At first order and OSR 64, the idealised gain is 54.2 dB, or 9.00 bits.

27.4 Overview: Two Ways to Spend Silicon – Speed vs Resolution

SAR and sigma-delta (ΣΔ) converters do the same job — turn a voltage into a code — but spend the silicon on opposite ends of the same trade. A SAR ADC runs a binary search: for an N-bit result it makes N comparisons against an internal DAC, one bit per clock, so one sample takes about N clocks and the answer is ready the moment the last bit is decided. A ΣΔ ADC instead runs a coarse (often 1-bit) quantizer very fast, then uses a digital filter to average that stream down into many effective bits.

Both share the same finest step: the least significant bit is LSB = Vref / 2^N. What differs is how each reaches that step and what it costs. A 12-bit SAR on an ESP32, STM32, or AVR converts in microseconds with no filter delay; a 24-bit ΣΔ like the HX711 (load cells) needs milliseconds because it trades sample rate for resolution.

Worked example. Suppose a 0–3.3 V pressure sensor outputs 1.65 V at half scale. A 12-bit SAR code is approximately round(1.65 / 3.3 * 4095) = 2048. One code is 3.3 / 4096 = 0.806 mV, so random jitter of three codes is only about 3 * 0.806 = 2.42 mV. That is fine for a pressure switch or a battery monitor. A load cell bridge is different: its full-scale signal may be only a few millivolts, so a 2.42 mV wobble can hide the measurement. That is where the slow ΣΔ path earns its keep.

SAR ADC

Binary search, N comparisons per sample. Fast (kSPS–MSPS), medium resolution (8–16 bit), low latency. Built into most microcontrollers.

Sigma-Delta

Oversample a 1-bit quantizer, then noise-shape and decimate. Slow (SPS–kSPS), very high resolution (16–24 bit), filter latency.

Resolution (LSB)

LSB = Vref / 2^N. For a 12-bit ADC at Vref = 3.3 V, the LSB is 3.3 / 4096 = 0.806 mV. Resolution is not accuracy.

Which When

Fast-changing signals (audio, vibration, motor) → SAR. Slow precision DC (strain, thermocouple, load cell) → ΣΔ.

27.4.1 Overview Knowledge Check

27.5 Practitioner: The Two Constraints That Bite in Real Circuits

Each architecture has one constraint that quietly ruins readings if ignored: the SAR needs its input to settle in time, and the ΣΔ (or any oversampling scheme) needs the right amount of noise and time to buy resolution.

Architecture	Hidden constraint	Practical rule
SAR	The sample-and-hold capacitor must charge through the source resistance before the first bit decision.	Keep source resistance low (single-digit kΩ or less) or add an op-amp buffer; otherwise lengthen the acquisition time.
Sigma-delta / oversampling	Extra bits cost samples and need dither noise to exist at all.	To gain `w` bits, sum `4^w` samples and shift right by `w`; throughput drops by `4^w`.

SAR settling. The internal sample cap charges with time constant τ = R_source × C_sample. To settle within half an LSB of an N-bit result the input needs about (N+1) × ln 2 time constants — roughly 9 time constants for a 12-bit conversion. If the sensor node is high-impedance (a resistor divider or a weak sensor output), τ is large, the cap never finishes charging in the acquisition window, and every reading reads low. This is why a high-impedance source needs a buffer ahead of the ADC, and it is the mechanism behind the "input impedance mismatch" pitfall.

To locate where source impedance becomes a conversion error, trace Figure 27.1 before applying the settling-time rule.

Figure 27.1: SAR ADC architecture showing analog input sampled by a sample-and-hold stage, compared against DAC feedback controlled by the SAR register, and emitted as a digital output code.

Follow Figure 27.1 from the analogue input into the sample-and-hold capacitor, then through the comparator, internal DAC feedback, and SAR register to the output code. The capacitor must settle before the first comparison; otherwise every later bit decision faithfully searches around the wrong held voltage. This connects the architecture to the practical contract: reduce source resistance, buffer the input, or lengthen acquisition time before trusting the advertised resolution.

Worked example — turning a 12-bit SAR into ~14 bits by oversampling. Averaging trades speed for resolution: to add w bits, take 4^w samples, sum them, and shift the sum right by w. For w = 2 that is 4^2 = 16 samples summed (max 16 × 4095 = 65520, a 16-bit sum) and shifted right by 2, giving a ~14-bit value — at 1/16 of the original sample throughput.

This only works if the signal carries at least about 1 LSB of noise. That noise acts as dither: it spreads a between-codes voltage across neighbouring codes, so the average lands between them. A perfectly clean, noise-free DC input sits on one code forever and averaging buys nothing.

27.5.1 Practitioner Knowledge Check

27.6 Under the Hood: Why a 1-Bit Converter Can Reach 24 Bits

A sigma-delta modulator feeds a coarse quantizer (often just 1 bit) from an integrator that is driven by the difference between the input and the fed-back quantizer output. That feedback loop has a crucial side effect: it shapes the quantization noise, pushing most of it up to high frequencies, out of the band where the signal lives. A digital low-pass decimation filter then throws that high-frequency noise away and drops the sample rate, leaving a high-resolution, low-rate output.

The numbers make the trade concrete. An ideal N-bit quantizer driven by a full-scale sine has SNR = 6.02 N + 1.76 dB (so each extra bit is worth about 6 dB). Oversampling spreads a fixed amount of quantization noise over a wider band, so the in-band noise falls:

Plain oversampling, no shaping: about +3 dB per octave of oversampling ratio — that is only +0.5 bit each time you double the sample rate (equivalently +1 bit per 4×).
First-order noise shaping: about +9 dB per octave — roughly +1.5 bits per doubling of the oversampling ratio.
Second-order noise shaping: about +15 dB per octave — roughly +2.5 bits per doubling.

Worked example. A first-order ΣΔ modulator sampled with oversampling ratio 64 has six doublings above base rate (2^6). At about 9 dB per doubling, the shaped-noise benefit is roughly 6 * 9 = 54 dB. Since one ideal bit is about 6.02 dB, that is close to 54 / 6.02 = 9 extra effective bits before real-world limits such as clock jitter, reference noise, and analog front-end noise reduce the result. Doubling the ratio to 128 adds one more octave, so the ideal gain is another 9 dB, or about 1.5 bits.

This is how a modulator with a 1-bit quantizer running at a high oversampling ratio, with second- or higher-order shaping, ends up delivering 20+ effective bits. A SAR, by contrast, does not average: each conversion is complete on its own, so its ceiling is set by DAC and comparator matching and by reference-voltage quality (the DNL/INL of the part), not by how long you oversample.

27.6.1 Under-the-Hood Knowledge Check

27.7 Choose an ADC for a Millivolt Bridge

For this ADC architecture, a pressure bridge changes by only a few millivolts while a nearby motor throws fast noise onto its cable. The converter choice must cover amplitude, rate, settling, and noise, not just the number printed after “bit.” In Figure 27.1, follow the external source through resistance and capacitance into the sample-and-hold node, then through the SAR decisions to the output code. At the converter resolution boundary, a code is trustworthy only after the input node has settled far enough.

In the millivolt architecture, for a 0–3.3 V, 12-bit ADC, one ideal step is (3.3/4096=0.000806\ \text{V}), or 0.806 mV. For this ADC architecture, a 6 mV bridge change spans only (6/0.806=7.44) ideal codes before noise and offset. Adding a gain of 100 would turn 6 mV into 0.600 V, but the amplifier’s offset, range, bandwidth, and saturation then enter the ADC architecture contract.

At the converter resolution boundary, oversampling does not create information from a fixed error. In the millivolt architecture, with suitable independent noise, averaging four samples cuts the random part by √4 and can add about one effective bit. A stable 3 mV offset remains 3 mV after any number of averages. A sigma-delta ADC may trade bandwidth for strong low-frequency resolution, while a SAR ADC may suit a faster multiplexed path; the pressure signal’s job decides which trade is useful.

27.7.1 Predict the Converter Result

The final ADC choice should state its usable input span, settled rate, measured noise, and allowed source resistance.

The bridge also sets a rate limit. If useful pressure changes end at 20 Hz, the ADC must sample above 40 samples/s before transition space is allowed. A practical rate needs room for the analogue filter to fall before Nyquist. At 200 samples/s, Nyquist is 100 Hz, leaving an 80 Hz transition band above the 20 Hz signal. The chosen ADC architecture must then deliver settled codes at that rate, not merely advertise a much faster serial clock.

Reference noise moves every ADC threshold because each code is measured as a fraction of that reference. A quiet 16-bit converter fed by a noisy 3.3 V rail can therefore lose useful resolution. The bridge, amplifier, reference, sample network, and ADC form one measurement chain.

Predict: The 12-bit reading jitters by three codes. About how much input voltage is that? Check: (3\times0.806=2.42\ \text{mV}), which can hide a small bridge change.
Predict: The sample time doubles and a high-resistance source moves closer to its final voltage. What ADC fault was reduced? Check: More acquisition time reduced sample-capacitor settling error.

27.8 Release Checklist

Before signing off an ADC architecture choice, verify that:

Work through the release evidence in order: The selected ADC architecture matches the signal: SAR for low-latency moderate-resolution signals, sigma-delta for slow precision DC, and flash only for extreme speed. LSB size is calculated from Vref / 2^N and compared with sensor accuracy, reference noise, and analog-front-end noise. SAR acquisition time is long enough for the source impedance and sample capacitor to settle within the target error band. Any high-impedance divider or sensor output is buffered, slowed, or sampled with an acquisition time supported by the data sheet. Oversampling budgets the 4^w sample-count cost for each additional effective bit and confirms that enough dither/noise exists. Sigma-delta latency, decimation-filter delay, and update rate are acceptable for the control loop or telemetry interval. Effective resolution is documented as ENOB or measured noise-free counts rather than copied from headline bit depth.

27.9 See Also

Follow these connections in order: How ADCs Work: Return to the main ADC fundamentals chapter for conversion flow, formulas, and selection context. Nyquist Sampling Theory: Connect converter choice to sample-rate and anti-aliasing requirements. ADC/DAC Worked Examples: Practice converter, reference, and resolution calculations in complete designs. Sensor Calibration Lab: Measure offset, gain, and noise once hardware is built. Sensor Fundamentals: Match sensor output range and impedance to the ADC front end.

27.10 Next

After the ADC architecture contract is explicit, continue with Nyquist Sampling Theory to choose sample rates and anti-aliasing filters for time-varying signals.