9 Low-Power Design: Leakage and Body Bias

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9.1 Start With the Decision

A transistor can leak even when it is off. Body bias and front-end noise decide if a tiny power budget will hold.

9.2 Route Overview

This is part 2 of 2. Review Low-Power Design: Sleep-State Energy Accounting for the preceding evidence.

9.3 Learning Objectives

Test subthreshold slope and the leakage-speed trade with a concrete scenario and pass criteria.
Validate concrete nanowatt adc and input amplifier with a concrete scenario and pass criteria.

9.4 Chapter Roadmap

Subthreshold Slope and the Leakage-Speed Trade
FD-SOI Forward and Reverse Body Bias
Low-Frequency Front-End Noise
Chopper Amplifier Signal Path
Concrete Nanowatt ADC and Input Amplifier
Summary
Key Takeaway

9.5 Subthreshold Slope and the Leakage-Speed Trade

A MOSFET does not become an ideal open switch when $V_{GS}$ crosses below threshold. In weak inversion, drain current is approximately exponential:

I_D\approx I_0\exp\!\left(\frac{V_{GS}-V_T}{nU_T}\right) \left(1-e^{-V_{DS}/U_T}\right),

where $U_T=kT/q$ is thermal voltage and $n\ge1$ is the subthreshold slope factor. For $V_{DS}$ more than a few thermal voltages, the final factor approaches one. Taking a base-10 logarithm gives

\log_{10}I_D=\text{constant}+\frac{V_{GS}-V_T}{nU_T\ln10}.

The subthreshold swing—the gate-voltage change needed for one decade of drain-current change—is therefore

S=\frac{dV_{GS}}{d(\log_{10}I_D)}=n\frac{kT}{q}\ln10.

At 300 K, $kT/q\approx25.85$ mV, so the ideal $n=1$ limit is $S\approx59.6$ mV/decade. The often quoted “60 mV per decade” is thus not simply $kT/q$ ; it includes $\ln10$ , and practical devices have $n>1$ . Higher temperature makes the slope worse.

Raising $V_T$ shifts the exponential curve and reduces off-current roughly by a decade per $S$ millivolts, but it also reduces overdrive $V_{GS}-V_T$ in the on state. Lower drive current increases delay. Low- $V_T$ devices are fast and leaky; high- $V_T$ devices are slower and quieter in standby. Multi-threshold libraries, power gating, and body bias allocate that trade by path instead of forcing one threshold on the whole chip.

Figure 9.1 turns that algebra into the picture worth memorizing: on a log current axis, “off” is a straight line that never reaches zero.

Plot of log drain current against gate-source voltage showing a low-threshold and a high-threshold transistor. Both subthreshold segments fall at about 100 millivolts per decade with a slope triangle marking one decade per 100 millivolts. Dashed lines mark off-currents of roughly 300 picoamps and 3 picoamps at zero gate voltage, while the on-currents at one volt differ far less. A note records the thermal floor of about 60 millivolts per decade at 300 kelvin, and a second card summarizes the low-threshold fast-but-leaky versus high-threshold quiet-but-slower trade. — Figure 9.1: Log drain current versus gate voltage for a low-VT and a high-VT device: parallel subthreshold slopes, off-currents decades apart, on-currents close together.

Follow either curve in Figure 9.1 down from its knee: the slope triangle marks one decade of current per 100 mV of gate voltage in this example device, and the floor pill records the thermal limit $S = n\cdot(kT/q)\cdot\ln 10$ near 60 mV per decade. At $V_{GS}=0$ the dashed reference lines sit at I_OFF low V_T $\approx$ 300 pA and I_OFF high V_T $\approx$ 3 pA — two decades apart — while at the right edge I_ON, low V_T beats the high-threshold device by only a modest margin. That asymmetry is the entire case for mixing thresholds per path.

9.6 FD-SOI Forward and Reverse Body Bias

Fully depleted silicon-on-insulator places a thin transistor body above a buried oxide. The body is depleted, and the isolated back gate can electrostatically shift threshold with less junction leakage than a conventional bulk body connection. Flipped-well layouts can make wider back-bias choices available for low-threshold devices, while regular-threshold arrangements use different well and nominal-bias connections. The exact safe rails—sometimes spanning several volts in a characterized FD-SOI process—are process rules, not portable firmware constants.

Define $V_{BS}=V_B-V_S$ . For an NMOS, forward body bias moves the body positive relative to the source and reduces $V_T$ ; reverse body bias moves it negative and raises $V_T$ . PMOS voltage signs reverse, so designers usually discuss the change in $|V_T|$ :

Bias mode	Threshold magnitude	On-current / speed	Off-current
Forward body bias	Lower $	V_T	$
Nominal bias	Characterized baseline	Baseline	Baseline
Reverse body bias	Higher $	V_T	$

Over a useful FD-SOI range, a first-order model is

\Delta V_T\approx-\eta\Delta V_{BS}

for NMOS under the sign convention above, where $\eta$ is the process-dependent body factor. Substituting the shifted $V_T$ into the weak-inversion equation shows why a modest reverse bias can reduce $I_{OFF}$ exponentially. Substituting it into an on-current model such as $I_{ON}\propto(V_{GS}-V_T)^\alpha$ shows the simultaneous loss of drive.

Figure 9.2 assembles the three views this section has been juggling: where the back gate physically sits, how bias moves the threshold, and what that shift does to the two currents.

Three-panel figure. A simplified FD-SOI cross-section shows source, thin fully depleted body and drain over a buried oxide, with the well beneath acting as a back gate driven by a body-bias voltage, and notes for flipped-well and regular-well variants. A plot of threshold magnitude against body-bias voltage falls from the reverse-bias region through nominal into forward bias. A log drain-current plot shows three curves: forward bias with more on-current and decades more off-current, nominal, and reverse bias with less of both. — Figure 9.2: FD-SOI body bias: the well under the buried oxide acts as a back gate; forward bias lowers the threshold for speed, reverse bias raises it for decades less leakage.

In the cross-section of Figure 9.2, the well = back gate layer sits under the BOX · buried oxide, so the V_BB contact steers the thin body electrostatically rather than through a junction — the reason added leakage stays small. The middle plot shows |V_T| falling as bias moves from the reverse bias (RBB) region through nominal into forward bias (FBB); the bottom plot then slides the whole transfer curve, fanning the off-currents across decades while the on-currents move by percent. That asymmetry is what an adaptive bias schedule exploits.

An adaptive policy can therefore apply forward bias for a deadline-bound active burst and reverse bias during a long retained sleep. It must budget bias-generator current, rail-settling time, reliability limits, temperature, and the energy of changing modes. Firmware should select only documented operating points and wait for the silicon’s ready indication; transistor cross-sections and well voltages belong to the chip’s process documentation.

9.7 Low-Frequency Front-End Noise

A sensor interface crosses two domains. The transducer and continuous-time signal conditioning amplify, translate, and anti-alias the signal before sampling. A sample-and-hold and ADC then create discrete-time codes for digital processing. Noise or drift introduced before conversion is digitized along with the signal; more ADC bits cannot remove it.

Figure 9.3 lays that chain out with the cost of each hop attached: every stage between the transducer and the digital word both adds noise and draws energy, and the budget must name both.

Six numbered stages from sensor to digital word. The sensor adds drift, flicker noise and pickup and costs excitation bias; the low-noise amplifier adds offset, flicker and thermal noise and costs standing bias current; the anti-alias filter stops alias fold-back; the sample-and-hold adds kT-over-C noise and costs charge per sample; the SAR ADC adds quantization and reference noise with per-conversion energy. A dashed sampling boundary separates continuous time from discrete time, and the final card notes everything added upstream is baked into the samples. — Figure 9.3: Anatomy of an analog-digital interface: sensor, low-noise amplifier, anti-alias filter, sample-and-hold, SAR ADC with reference, and the digital word — each stage annotated with its noise contribution and energy cost.

Track the numbered cards of Figure 9.3 downward: the Low-noise amplifier stage carries the offset + 1/f + thermal chip this section quantifies next, and the dashed sampling boundary between the anti-alias filter and the Sample-and-hold is where continuous time ends. Below that line the converter contributes kT/C and quantization terms of its own, and the closing card states the rule the whole budget rests on: everything added upstream is baked into the samples.

MOS amplifiers have approximately white thermal-noise density above a corner frequency and rising flicker, or $1/f$ , noise below it. A common input-referred model is

S_v(f)=S_{white}+\frac{K_f}{f^\alpha},\qquad \alpha\approx1.

The corner $f_c$ is where $K_f/f_c^\alpha=S_{white}$ . Below $f_c$ , integrating flicker noise over $f_L$ to $f_H$ for $\alpha=1$ gives

v_{n,rms}^2=\int_{f_L}^{f_H}\frac{K_f}{f}\,df =K_f\ln\!\left(\frac{f_H}{f_L}\right).

DC offset and slow temperature drift occupy the same low-frequency region as bridge sensors, thermocouples, biopotentials, and other slowly varying signals. If the signal spectrum sits below $f_c$ , the amplifier’s offset, drift, and flicker noise can swamp it before the ADC sees a useful separation. The review must therefore compare input-referred signal range, offset after calibration, integrated noise across the actual bandwidth, and ADC LSB size at the amplifier output.

9.8 Chopper Amplifier Signal Path

Chopper stabilization separates a low-frequency input from the amplifier’s own low-frequency error by multiplying twice with a square wave $m(t)\in\{-1,+1\}$ .

The first mixer forms $x_m(t)=x(t)m(t)$ . A baseband sensor signal moves to odd harmonics of chopping frequency $f_{chop}$ .
The amplifier processes that modulated signal. Its offset and internal $1/f$ noise are added after the first mixer and therefore remain near baseband at this point.
The second synchronous mixer multiplies by the same phase. Because $m^2(t)=1$ , the wanted signal returns to baseband: $x(t)m(t)m(t)=x(t)$ .
The amplifier offset and low-frequency noise are multiplied only once, so they move to $f_{chop}$ and its odd harmonics.
A low-pass filter passes the recovered sensor band and rejects the translated error and switching artifacts.

An ideal 50% square wave has odd-harmonic coefficients proportional to $1/(2k+1)$ , so the first modulation produces replicas around $f_{chop},3f_{chop},5f_{chop},\ldots$ . Choose $f_{chop}$ comfortably above the signal band and the amplifier’s flicker corner, while leaving enough amplifier bandwidth and filter separation for settling.

The five numbered steps become visible in Figure 9.4, which pins all three spectra to one shared frequency axis so the swap is impossible to miss.

Figure 9.4: The chopper path — mixer, amplifier, mixer, low-pass filter — and the spectrum at three points: the signal rides out to odd harmonics of f_chop and back, while offset and 1/f noise make only the outward trip.

In the path card of Figure 9.4 the error term V_os + 1/f noise enters after the first mixer — that ordering is the entire trick. Panel 2 shows the wanted signal parked at f, 3f, 5f — odd harmonics while the amplifier’s own error sits at DC; after the second multiply, panel 3 shows the signal home at baseband inside the LPF passband and the error parked at odd harmonics where the filter excludes it. The small gray chop artifacts at even harmonics are the residue real switches add.

Chopping is not magic. Input noise that exists before the first mixer follows the wanted signal back to baseband. Switch charge injection, clock feedthrough, finite gain-bandwidth, and phase mismatch create ripple and residual offset. Measure input-referred noise, ripple spectrum, overload recovery, and settling over the complete sampling window.

9.9 Concrete Nanowatt ADC and Input Amplifier

A 1 ksample/s converter has a 1 ms sample period. If its successive-approximation activity occupies 5 $\mu$ s and the circuitry is idle for the remaining 995 $\mu$ s, the active duty factor is

d=\frac{5\ \mu\text{s}}{1\ \text{ms}}=0.005=0.5\%.

An average converter power of 1 nW at 1 ksample/s corresponds to

E_{conversion}=\frac{1\ \text{nJ/s}}{1000\ \text{conversions/s}} =1\ \text{pJ/conversion}.

If off-state power were negligible, the equivalent active power during the 5 $\mu$ s window would be $1\ \text{nW}/0.005=200$ nW. A real ledger must keep clock generation, reference settling, leakage, tracking, and output logic in the appropriate window rather than attributing everything to the comparator search.

The paired input amplifier provides a separate lesson. A gain of 32 dB is

A_v=10^{32/20}=39.8\ \text{V/V}.

AC coupling blocks sensor and electrode DC offsets from consuming output range, while a slow DC-servo loop feeds back the residual output baseline so the signal path remains centered. The servo corner must sit below the wanted band; otherwise it will cancel part of the signal. A stated 370 Hz bandwidth then bounds the upper useful signal content and informs anti-alias filtering before 1 ksample/s conversion.

The reported input-referred noise of 26 $\mu$ V rms becomes about

v_{n,out}=39.8(26\ \mu\text{V})=1.03\ \text{mV rms}

at the amplifier output. Its reported total current of 1 nA corresponds to 1 nW only at a 1 V supply; at supply $V_{DD}$ the power is $V_{DD}\times1$ nA. These measured values close the design only after checking signal amplitude, noise bandwidth, servo settling, ADC input range, temperature drift, and the energy of every supporting reference and clock. The result is compelling precisely because it is a complete front-end timing and noise contract, not because “nanowatt” appears on one block.

Figure 9.5 draws both halves of that contract — the converter’s schedule and the amplifier’s loop — with the measured numbers attached where a reviewer would check them.

Two cards. A timeline of one millisecond shows a thin 5 microsecond conversion sliver, a tracking-idle span of 995 microseconds, a zoom strip of the conversion burst, and chips reading duty 0.5 percent, 1 picojoule per conversion, 1 nanowatt average, with a note that conversion itself runs near 200 nanowatts. A block diagram shows an AC-coupled input, two amplifier stages, and a slow DC servo feeding the output baseline back to the input node, with chips for 32 decibel gain, 370 hertz bandwidth, 26 microvolt rms input noise and about 1 nanoamp supply current. — Figure 9.5: A nanowatt front end as two contracts: a SAR ADC active for 5 µs of every 1 ms sample period, and an AC-coupled 32 dB amplifier whose slow DC servo returns the output baseline to the input.

The timeline card of Figure 9.5 shows why the average deceives: the tracking / idle span owns 995 µs of every millisecond, and the zoom strip compresses the entire conversion into one 5 µs burst — the chips beneath restate the 0.5% duty and 1 pJ per conversion behind the 1 nW average. In the amplifier card, the DC servo · slow block feeds the output baseline back to the input node behind the AC coupling, which is what lets a 39.8 V/V stage spend its whole output range on signal instead of on electrode offset.

9.10 Summary

This chapter covers low-power strategies including sleep-mode selection, duty-cycle policy, peripheral power gating, firmware timing discipline, radio batching, and voltage or clock scaling.

9.11 Key Takeaway

In the field, optimize charge per useful outcome. Sleep modes, power gating, batching, retry limits, and firmware timing should be selected from measured traces and failure-mode requirements.

9.12 Continue Your Route

This final part closes the route from Subthreshold Slope and the Leakage-Speed Trade through Key Takeaway. Return to Low-Power Design: Sleep-State Energy Accounting or continue from the energy-power module index.