7 Low-Power Design: Duty-Cycle Energy Accounting

7.1 Start With the Decision

Use duty-cycle math as a review ledger, not as a slogan.

7.2 Route Overview

This is part 2 of 2. Review Low-Power Design: Firmware and Wake Policies for the preceding evidence.

7.3 Learning Objectives

• Calculate folded duty-cycle math notes from stated measurements and limits.
• Validate label the strategy stack with a concrete scenario and pass criteria.

7.4 Chapter Roadmap

• Folded Duty-Cycle Math Notes
• Low-Power Transition Cost Calculation Audit
• Checkpoint: Duty-Cycle Ledger
• Peripheral Power Gating
• Firmware Timing Discipline
• Radio and Data Strategy
• Batch
• Filter
• Bound Retries
• Separate Health From Data
• Clock and Voltage Scaling
• Measurement Checklist
• Checkpoint: Load And Firmware Control
• Common Pitfalls
• 1. Choosing Deep Sleep Without Counting Reinitialization
• 2. Leaving External Loads Powered
• 3. Using Delay Loops Instead Of Sleep
• 4. Optimizing Peak Current Instead Of Charge
• 5. Forgetting Failure Modes
• Checkpoint: Release Evidence
• Knowledge Check
• Knowledge Check: Choosing A Sleep Mode
• Match Strategies To Purpose
• Order The Low-Power Review
• Label The Strategy Stack
• Related Chapters
• What’s Next
• Continue to Part 2

7.5 Folded Duty-Cycle Math Notes

Use duty-cycle math as a review ledger, not as a slogan. The basic average-current estimate is:

I_avg = (I_active * t_active + I_sleep * t_sleep) / (t_active + t_sleep)

That estimate is only useful when the measurement record includes wake time, sensor stabilization, radio join time, retries, queue flushes, and the real sleep current of the whole board. Sleep current often dominates long-life designs: a small always-on regulator, pull-up, LED, sensor rail, or wake circuit can erase the benefit of a shorter active window.

Current-only math is a shortcut, not the definition of energy. It is defensible when all compared states use the same rail and regulator path; it is risky when battery voltage changes, a regulator burns the difference as heat, or the MCU is allowed to run across a wide supply range. In those cases, convert the state ledger to power or charge at the actual rail conditions before turning it into a battery-life claim.

Treat transition time as its own ledger term when the wake period is short. A BLE node that wakes once per second might sleep for about 999.6 ms at 4.8 uA, transmit and run the CPU for 0.3 ms at 14.6 mA, and spend another 0.14 ms moving the radio into transmit at 7 mA. The transition term is only about 1 uA-s, but it sits next to a sleep term of about 4.8 uA-s and an active term of about 4.4 uA-s. Leaving it out can make the cycle look roughly ten percent cheaper than the device actually measures.

7.6 Peripheral Power Gating

The MCU may be in deep sleep while sensors, pull-ups, level shifters, indicators, or a radio module continue drawing current. A low-power design needs a load inventory.

To decide whether peripheral power gating is defensible, first locate sleep control and Load in the figure at Figure 7.1. They expose the two conditions that the surrounding argument must keep together.

Find sleep control on Figure 7.1; it exposes the energy consequence. Now contrast Load, which adds a distinct review condition, with switch, which adds a distinct review condition. That contrast is the visual’s teaching load: No-panel peripheral power-gating path showing MCU control, load switch, sensor rail, discharge path, and reinitialization after wake. The chapter can now use peripheral power gating without dropping the conditions shown here.

7.7 Firmware Timing Discipline

Low-power firmware should make the active window short, deterministic, and measurable.

// Pseudocode pattern for a measured low-power cycle.
wake_cause = read_wake_cause();
start_trace_marker("wake");

enable_required_rails();
wait_for_sensor_settle();
sample = read_sensor();

if (should_report(sample, wake_cause)) {
    radio_on();
    send_batched_report(sample);
    radio_off();
}

disable_required_rails();
save_minimal_state();
schedule_next_wake();
enter_sleep();

Keep the active path boring. Avoid unbounded retries, blocking delays, unnecessary scans, debug output, and initialization work that could have been cached or skipped safely.

7.8 Radio and Data Strategy

The radio is often the highest-current state, but the fix is not always “use a different radio.” First reduce avoidable radio-on time.

Cellular batching is the same fixed-cost problem with a larger state machine. An LTE-style modem may move from idle into continuous reception, then through short and long DRX windows before it can return to the low floor. If the application can send two small records every 60 seconds instead of one small record every 30 seconds, the useful payload doubles while the expensive on, listen, tail, and release path is paid less often. Accept that trade only when the added data age is inside the service contract and the batch still preserves sequence numbers, alarm flags, and retry evidence.

Short-range radios need the same state ledger. A sender pays transmit electronics and the RF power amplifier; a receiver pays receive electronics and often idle-listening time; the channel adds path loss and required SNR based on rate, BER target, and modulation. At long range, RF transmit energy may dominate. At very short range, receiver electronics, startup, acknowledgments, and listening windows can dominate instead.

Use technology tables as review prompts, not universal rankings:

For an embedded endpoint, “where the power goes” depends on the workload. One design may spend most calendar time asleep while a small transmit slice dominates charge; another may spend the budget in sensor warm-up or LEDs. Start with a back-of-the-envelope state budget, then validate it with real power measurements for sleep, sensing, transmit, receive, retry, and recovery states. The pie chart is not proof until the measured trace agrees with it.

7.13 Clock and Voltage Scaling

Dynamic voltage and frequency scaling can reduce instantaneous power, but it is not automatically an energy win. If lower frequency stretches the active window enough, the total energy may stay the same or increase.

Use clock or voltage scaling when:

• The workload has slack before the next deadline.
• The lower-power mode still finishes and returns to sleep early.
• Peripheral timing, radio deadlines, ADC accuracy, and bus clocks remain valid.
• The before/after trace shows lower charge per cycle, not just lower peak current.

Do not use it as a substitute for sleep, power gating, or radio batching.

Clock selection is also a firmware evidence item, not just a datasheet feature. A SAM4L-style Cortex-M design may expose run, sleep, wait, and retention modes, plus clock sources such as a 32 kHz oscillator, a 116 kHz system clock, a 1 MHz RC clock, and a 12 MHz fast RC clock. Use the slowest source or divider that still meets UART, SPI, ADC, radio, and interrupt timing requirements, then record the current and wake latency for that exact mode. Vendor-specific low-power states and clock trees are not portable across MCU families, so the review record should name the silicon, enabled clocks, retained peripherals, and measured charge per useful cycle. The same record should justify cost: a larger MCU or SoC may save active energy for one workload, but it still needs evidence that the added memory, buses, accelerators, or radio features are worth their price and sleep-floor consequences.

7.14 Measurement Checklist

7.15 Common Pitfalls

7.16 Knowledge Check

7.17 Knowledge Check: Choosing A Sleep Mode

7.18 Match Strategies To Purpose

7.19 Order The Low-Power Review

7.20 Label The Strategy Stack

7.21 Related Chapters

7.22 What’s Next

7.23 Continue to Part 2

Continue with Low-Power Design: Sleep Depth and Hidden Leakage.

7.24 Continue Your Route

This final part closes the route from Folded Duty-Cycle Math Notes through Continue to Part 2. Return to Low-Power Design: Firmware and Wake Policies or continue from the energy-power module index.