Measure I2C pull-up rise time

Steps

Screens captured against Falstad CircuitJS Falstad CircuitJS live in Playwright Chromium 151.0.7922.34 on 2026-10-08; simulation time step 5 ns; no simulator version exposed on 2026-10-08; the tool may have moved on — the text steps are the contract.

1. 1 Step 1

   Do

   In the Falstad circuit canvas, open the 2.2 kΩ circuit. Identify the 3.3 V source, pull-up, 100 pF bus capacitor, and n-MOSFET sink driven at 100 kHz.

   You will see

   The 3.3 V source feeds the 2.2 kΩ pull-up. The bus capacitor is 100 pF. The gate source switches between 0 and 5 V at 100 kHz. The bottom scope traces the bus voltage.

   Why it matters

   The synthetic design case has seed 1 and no random draws. The MOSFET pulls low; the resistor charges the capacitance after release.

2. 2 Step 2

   Do

   In the Falstad circuit canvas, on the scope, locate a rising edge after the sink releases. Record the 0.99 V and 2.31 V crossing times from the running CircuitJS element voltage. For a repeatable readout, use the CircuitJS Console recipe at /practice/i2c-pullup-rise-time/README.md.

   You will see

   For 2.2 kΩ: 30% crossing 5.085 µs; 70% crossing 5.275 µs. The difference is 190 ns at a 5 ns simulator step. The bus approaches 3.3 V after release.

   Why it matters

   The 30–70% interval is the I2C rise-time comparison; quoting both crossings makes the measured difference checkable.

3. 3 Step 3

   Do

   In the Falstad circuit canvas, open the 4.7 kΩ circuit with the same 3.3 V, 100 pF, 100 kHz sink and scope setting. Read the next rising edge.

   You will see

   For 4.7 kΩ: 30% crossing 5.175 µs; 70% crossing 5.575 µs. The measured rise is 400 ns. The visible scope edge is slower than the 2.2 kΩ case.

   Why it matters

   Only the pull-up changes, so a longer charge interval can be attributed to the higher resistance in this model.

4. 4 Step 4

   Do

   In the Falstad circuit canvas, open the 10 kΩ circuit, keeping the bus capacitance and sink waveform fixed. Measure the same two voltage crossings.

   You will see

   For 10 kΩ: 30% crossing 5.365 µs; 70% crossing 6.215 µs. The measured rise is 850 ns. The scope shows the longest rounded edge of the three runs.

   Why it matters

   The larger resistor weakens the pull-up, increasing the time the bus spends between logic thresholds.

5. 5 Step 5

   Do

   In the Falstad circuit canvas, compare the three recorded 30–70% rises with NXP UM10204 Rev. 7.0, timing table: Standard-mode maximum 1000 ns and Fast-mode maximum 300 ns.

   You will see

   CircuitJS measured 190 ns (2.2 kΩ), 400 ns (4.7 kΩ), and 850 ns (10 kΩ). All three are below 1000 ns; only 2.2 kΩ is below 300 ns. NXP table values are 1000 ns and 300 ns.

   Why it matters

   The model isolates pull-up and capacitance. Check real sink-current, device pins, and waveform margins before choosing a board resistor.