ADC Sampling and Quantization

Watch a sensor voltage become timed samples, held values, quantized ADC codes, and a staircase digital signal.

A beginner-first ADC sampling and quantization workbench with synchronized analog waveform, sample-and-hold cursor, quantization steps, digital code, alias warning, and practical sensor-fit feedback.

Animation ADC Sampling

ADC Sampling and Quantization

Step through a sensor voltage as it is sampled in time, held long enough for conversion, rounded to the nearest ADC level, and emitted as a digital code.

AnalogPipeline stage

Code 0Digital output

206.3 mV1 LSB

SafeSampling check

Colour keyFundamentals identityanalog inputsampled datasafe samplingalias/error

Try

Choose 4-bit Resolution and a 24 Hz Sample rate. Set Signal frequency at 3 Hz before taking one Step.

Observe

Follow the held voltage, Digital output, and quantization error after each Step. If Sample rate falls below twice Signal frequency, the Sampling check reports alias risk.

Explain

Sample rate discretises time; Resolution separately assigns each held voltage to one of 2^N codes. Too few time samples cause aliasing, whereas finite code width creates the staircase error.

Technical boundaries

The waveform uses deterministic teaching noise and ideal quantization; analog anti-alias filters, ADC settling, INL/DNL, jitter, clipping recovery, and hardware reference drift are omitted.

Sensor Scenario

Slow potentiometer uses a low-frequency signal and moderate sample rate, so sampling is safe and quantization is easy to inspect.

View Mode

Pipeline view explains what each stage does to one sample.

Playback

Play speed 900 ms

ADC Knobs

Resolution 4 bit

Sample rate 24 Hz

Signal frequency 3 Hz

Noise Low

Reference 3.3 V

Analog: the sensor voltage is continuous. It can take any value between 0 V and the ADC reference.

Sampling is safe.Time-domain check

16 codes available.Quantization check

Default setting is good for learning.Learning diagnosis

ADC Pipeline View

The analog curve, sample dots, held value, quantized staircase, code register, and error line stay synchronized with the selected stage.

Stage 1 of 5 Analog -> Sensor voltage

Conversion Evidence

The selected stage explains what changes between the real voltage and the emitted digital code.

Sampling Check

Nyquist compares sample rate with signal frequency.

Safe

Quantization Check

Bit depth and reference voltage decide how large each ADC step is.

16 levels

Sensor Fit

Compares quantization step, noise, and useful signal span.

Teaching fit

Beginner Ramp

Sampling answers when to measure. Quantization answers which numbered voltage step the measurement lands on. A good ADC design needs both a high-enough sample rate and small-enough voltage steps.

Pipeline Sequence

1. Sensor outputs a continuous voltage.
2. Sample clock chooses a moment in time.
3. Sample-and-hold keeps that voltage steady during conversion.
4. ADC maps the held voltage to a code.
5. Firmware receives the integer code and converts it back to engineering units.

Nyquist Rule

For a simple signal, sample at least twice the highest frequency component. Real systems add margin and use an analog anti-alias filter because sensors and noise rarely contain only one perfect frequency.

Formula Reference

• Levels = 2^N for an N-bit ADC.
• Teaching LSB = Vref / 2^N.
• Code = round(Vin / LSB), clamped to 0 through 2^N - 1.
• Ideal quantization error is usually within +/- 0.5 LSB, except near rails.

Noise vs Resolution

More bits create smaller steps, but noisy sensors and unstable references can still make readings jump. If noise is larger than the LSB, averaging or filtering may matter more than buying a higher-bit ADC.

Practical IoT Note

Microcontrollers often expose 10-bit or 12-bit ADCs, but effective accuracy can be lower. Match the reference range to the sensor output, keep wiring quiet, and avoid sampling faster than the signal chain can settle.

Practice 1

Use Slow Potentiometer. Step through the pipeline and identify where the analog value becomes an integer code.

Practice 2

Switch to Aliasing Demo. Lower sample rate below twice the signal frequency. What warning appears and why?

Practice 3

Increase resolution from 4 bit to 10 bit. What happens to LSB size and quantization error?

Related Study

Quantization and FilteringReview ADC resolution and digital filters. Signal ProcessingConnect sampling to Nyquist and aliasing. ADC Resolution VisualizerCompare bit depth, reference, and noise. Sampling VisualizerExplore aliasing and data-rate trade-offs.