Math Bridge: ADC Sampling and Quantisation

← Back to ADC Fundamentals
Math BridgeIoT FundamentalsStruggle-friendly runway

How do time samples and voltage codes fail differently?

Keep the Nyquist and alias checks separate from code width, half-code error, span use, and ideal SNR.

Sammy, the maths guideSammy guides
The one targetSeparate aliasing from quantisation.
The chapter case40 Hz, two alias examples, and a 12-bit 3.3 V ADC.
What it buys youA sampling and resolution plan with distinct evidence.

A field team has a real problem to settle: How do time samples and voltage codes fail differently? They must decide what happens before they change adc bits on the device. Predict the direction first.

See the relationship first

The figure reads from left to right. The blue card is adc bits. The middle card uses this page's rule. The green card is minimum sample rate. Follow the arrows: set the input, use the rule, then read the result and its unit.

The audit later on checks more than one number. Here, the added model uses the baseline named below and holds every other chapter value fixed. That sentence bridges the fixtures, so the numbers do not change without a reason.

ADC bits changes minimum sample rate An input card leads through the page rule to the minimum sample rate result. SET INPUT ONE CONTROL USE RULE predict calculate check units READ RESULT
Follow the arrows. Bit depth partitions voltage. Sample rate partitions time. Each control can improve one axis while leaving the other failure untouched.

Derive the baseline in four moves

  1. 1

    Name the input. The chapter baseline for adc bits is 12.

  2. 2

    Name the rule. fs,min=2x40=80 samples/s |90-1x100|=10 Hz |1200-1x1000|=200 Hz levels=2^12=4096 q=3.3/4096=0.806 mV; q/2=0.403 mV SNRideal=6.02x12+1.76=74.0 dB

  3. 3

    Put in the chapter value. Set adc bits to 12. The page rule gives minimum sample rate as 80 Hz.

  4. 4

    Read the result. Keep Hz next to the value. Use it only within the limits on this page.

Predict, then change adc bits

Try Predict what happens to minimum sample rate. Move one control, calculate, then check your idea.

12
Chapter baseline
Minimum sample rate

Observe Bit depth partitions voltage. Sample rate partitions time. Each control can improve one axis while leaving the other failure untouched. Reset to 12 and compare minimum sample rate.

Explain Only adc bits moves here. The other chapter values stay fixed.

Check yourself

What should you do before you trust the result?
Answer: Predict its direction, use the shown rule, keep the units, and reset to the worked baseline.
What does this small model leave out?
Answer: Only adc bits moves. Field effects named in the page limits stay fixed.

Honesty note. This teaching model changes only adc bits. It replays the chapter baseline; it is not a field prediction.

1. Start with the physical story

Sampling chooses moments in time. If the clock is too slow, a fast input can appear as a false slower signal. Quantisation happens after sampling and rounds each captured voltage to one of a finite number of codes.

Sammy: More bits cannot repair an alias, and a faster clock does not automatically give smaller voltage codes.

2. Name every algebra move

1

Set NyquistDouble the highest useful signal frequency.

2

Fold a toneSubtract the nearest whole multiple of sample rate and take the magnitude.

3

Count levelsRaise two to the number of bits.

4

Find one codeDivide 3.3 V by the level count.

5

Translate resolutionDivide code width by 10 mV per degree C.

6

Estimate the ideal ceilingUse 6.02N+1.76 dB.

3. Reproduce the chapter case

fs,min=2×40=80 samples/s
|90−1×100|=10 Hz
|1200−1×1000|=200 Hz
levels=2^12=4096
q=3.3/4096=0.806 mV; q/2=0.403 mV
SNRideal=6.02×12+1.76=74.0 dB

The 1.65 V conditioned span uses 2048 codes at 12 bits, while each code represents about 0.0806 degrees C at 10 mV per degree C.

4. Try one real input

TryChange ADC bit depth and predict code width and ideal SNR. Watch the alias results stay fixed.

ADC bits
Minimum sample rate
90 Hz alias
1200 Hz alias
Code levels
One code
Half-code bound
Temperature step
Conditioned-span codes
Ideal SNR

ObserveAt 12 bits, doubling the level count requires one more bit, but neither stored alias changes because their sample rates did not change.

ExplainBit depth partitions voltage. Sample rate partitions time. Each control can improve one axis while leaving the other failure untouched.

Technical boundaries.

These are ideal converter and discrete-time bounds.

Filter
Nyquist equality leaves no transition band for a real anti-alias filter.
ADC
Noise, reference drift, non-linearity, source impedance, and jitter reduce effective bits.
Sensor
Code width is not the same as calibrated accuracy.

Correct, not complete: sample rate and nominal bits do not prove end-to-end measurement quality.

5. Use the result in the design

Set a passband, choose filter margin and sample rate together, then measure input-referred noise and calibrated error in physical units.

6. Record the evidence state

Keep signal band, interferers, filter response, sample clock, reference, bit depth, input span, source impedance, measured SNR, ENOB, calibration, and temperature.

7. Check yourself

Why does 90 Hz appear at 10 Hz when sampled at 100 samples/s?
Answer: It folds around the nearest sample-rate copy: |90−100|=10 Hz.
What happens to code width when one bit is added?
Answer: The level count doubles, so ideal code width halves.
Does a 0.0806 degree C code prove that accuracy?
Answer: No. Sensor, reference, noise, linearity, and calibration errors remain.
Honesty boundary.

The calculations reproduce the chapter's ideal sampling and ADC constants.

Filter
Nyquist equality leaves no transition band for a real anti-alias filter.
ADC
Noise, reference drift, non-linearity, source impedance, and jitter reduce effective bits.
Sensor
Code width is not the same as calibrated accuracy.

Correct, not complete: sample rate and nominal bits do not prove end-to-end measurement quality.

Return to ADC Fundamentals with the maths unpacked →