Math Bridge: Three Sampling Limits

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Math BridgeSensorsStruggle-friendly runway

Which sampling limit are you hitting?

One thread that keeps conversion time, aliasing, and ADC rounding separate.

Phoebe, the physics guidePhoebe guides
The one targetName the failed limit before fixing it.
The chapter caseDHT22, BMP280, and a 12-bit ESP32 range.
What it buys youAvoid filters and polling changes that cannot help.

A field team faces an unresolved physical question: Which sampling limit are you hitting? They must answer it before changing analogue sample rate in hertz on the real device. Predict the direction first.

See the relationship before changing it

The figure reads from left to right. The blue card is analogue sample rate in hertz. The middle card applies this page's relationship. The green card is apparent 60 hz component. Walk the arrows once: set the input, apply the rule, then read the result with its unit.

The retained audit below checks several chapter fixtures. This added model holds every other chapter fixture fixed, so the numeric fixture does not switch without explanation.

Analogue sample rate in hertz changes apparent 60 hz component An input card leads through the page relationship to the apparent 60 hz component result. SET INPUT ONE CONTROL APPLY RULE predict calculate check units READ RESULT
Walk the arrows. Raise the analogue rate through 120 samples/s and the alias stops. That does not make the DHT22 convert faster or shrink the ADC's voltage bins.

Derive the baseline in four named moves

  1. 1

    Name the input. The chapter baseline for analogue sample rate in hertz is 100.

  2. 2

    Name the relationship. fN=fs/2; falias=|nfs-f|; q=VFSR/2^N; Tconvert=1/fconvert

  3. 3

    Substitute the chapter fixture. Set analogue sample rate in hertz to 100. The page ledger gives apparent 60 hz component as 40 Hz.

  4. 4

    Read the result. Keep Hz beside the value. Use it only inside the technical boundary on this page.

Predict, then change analogue sample rate in hertz

Try Predict the direction of apparent 60 hz component. Move one control, calculate, then check your prediction.

100
Chapter baseline
Apparent 60 Hz component

Observe Raise the analogue rate through 120 samples/s and the alias stops. That does not make the DHT22 convert faster or shrink the ADC's voltage bins. Reset the control to 100 and compare apparent 60 hz component.

Explain Only analogue sample rate in hertz moves here. The other chapter fixtures remain fixed.

Check yourself

What should you do before trusting a moved-control result?
Answer: Predict its direction, apply the shown relationship, keep the units, and reset to the worked baseline.
What does this small model leave out?
Answer: Only analogue sample rate in hertz moves. Field effects named in the page's technical boundary stay fixed.

Honesty note. This teaching model changes only analogue sample rate in hertz. It replays the chapter fixture; it is not a field prediction.

1. Split time from amplitude

A sensor may finish conversions slowly. A sampled analogue signal may alias. An ADC may round voltage. These are three different information losses.

Phoebe: The word sampling is not a diagnosis. Name the ruler and the failure.

2. Conversion time is a ready clock

Tconvert=1/fconvert

The chapter's DHT22 rate is 0.5 Hz, so one fresh result takes 2 s. Polling every 0.5 s cannot force four new physical measurements.

3. Nyquist and ADC bins are different

fNyquist=fs/2; falias=|nfs−f|
q=VFSR/2^N; σq=q/√12

Nyquist limits the frequency that time samples can preserve. Quantisation limits the voltage change that amplitude bins can report.

4. Try an analogue sample rate

fN=fs/2; falias=|nfs−f|; q=VFSR/2^N; Tconvert=1/fconvert

TrySample a stated 60 Hz teaching signal while the chapter's 3.6 V, 12-bit ADC, 157 Hz BMP280 rate, and 0.5 Hz DHT22 rate stay fixed.

Nyquist ceiling
Apparent 60 Hz component
ADC code step
ADC RMS floor
Ideal ADC ceiling
BMP280 Nyquist ceiling
DHT22 fresh interval

ObserveAt 100 samples/s, Nyquist is 50 Hz, so the stated 60 Hz analogue component appears at 40 Hz. The 0.879 mV code step and 2 s DHT22 interval do not change.

ExplainRaise the analogue rate through 120 samples/s and the alias stops. That does not make the DHT22 convert faster or shrink the ADC's voltage bins.

Technical boundaries.

The 60 Hz component is an explicit teaching signal, not a DHT22 claim.

analogue bandwidth
Needs separate evidence
front-end filtering
Needs separate evidence
ESP32 effective resolution and range differ from ideal nominal bits
Needs separate evidence
Sensor digital filtering and output-data-rate rules belong to their datasheets
Needs separate evidence

Use field evidence or a deeper model before release.

5. Reproduce the fixed chapter numbers

3.6 V/4096=0.879 mV; 0.879/√12=0.254 mV; SNRideal=74.0 dB
157/2=78.5 Hz; 1/0.5=2 s

6. Choose the matching repair

Wait for data-ready when conversion time is the limit. Raise sample rate and add an analogue anti-alias filter for bandwidth. Change range, bits, gain, or noise design for amplitude resolution.

7. Check yourself

Why does polling a DHT22 faster return stale codes?
Answer: The part has not completed a new conversion; the limit is its ready interval.
Why does 60 Hz appear as 40 Hz at 100 samples/s?
Answer: It is above the 50 Hz Nyquist ceiling and folds to |100−60|=40 Hz.
Can more ADC bits repair an alias?
Answer: No. More bits refine amplitude bins after the time-domain fold has already happened.
Honesty boundary.

These are the chapter inputs, worked results, and named teaching assumptions.

3.6 V
Voltage or voltage-step value
12-bit
Digital resolution or converter setting
157 Hz
Frequency, sample rate, or event rate
0.5 Hz
Frequency, sample rate, or event rate
60 Hz analogue component is labeled teaching input
Named teaching assumption

The page distinguishes ideal limits; it does not claim every sensor front end exposes its raw bandwidth.

Return to the chapter with the maths unpacked →