Phoebe guidesA field team faces an unresolved physical question: Why 24 bits cannot rescue 2% accuracy They must answer it before changing adc resolution in bits on the real device. Predict the direction first.
See the relationship before changing it
The figure reads from left to right. The blue card is adc resolution in bits. The middle card applies this page's relationship. The green card is code step. Walk the arrows once: set the input, apply the rule, then read the result with its unit.
The retained audit below checks several chapter fixtures. This added model holds every other chapter fixture fixed, so the numeric fixture does not switch without explanation.
Derive the baseline in four named moves
- 1
Name the input. The chapter baseline for adc resolution in bits is 24.
- 2
Name the relationship. q=Vref/2^N; σq=q/√12; gap=SNRADC-20log10(1/ε)
- 3
Substitute the chapter fixture. Set adc resolution in bits to 24. The page ledger gives code step as 196.7 nV.
- 4
Read the result. Keep nV beside the value. Use it only inside the technical boundary on this page.
Predict, then change adc resolution in bits
Try Predict the direction of code step. Move one control, calculate, then check your prediction.
Observe Adding bits keeps lowering the rounding floor while the sensor's 2% bias line stays still. Reset the control to 24 and compare code step.
Explain Only adc resolution in bits moves here. The other chapter fixtures remain fixed.
Check yourself
What should you do before trusting a moved-control result?
What does this small model leave out?
1. Name two different errors
Quantisation rounds voltage into one of 2^N bins. Accuracy says how far the sensor's calibrated response can sit from the physical reference.
2. Derive the ADC floor
Count levelslevels=2^N.
Find one stepq=Vref/2^N.
Uniform RMSσq=q/√12 and SNRADC≈6.02N+1.76 dB.
3. Put accuracy on the same dB scale
For fractional accuracy ε, compare full scale with that error fraction.
Subtract the two dB figures for the gap. Convert the gap back to an amplitude ratio with 10^(gap/20).
4. Try the ADC bits
TryAdd converter bits while keeping the chapter's 2% sensor accuracy fixed.
ObserveAt 24 bits, q≈197 nV, σq≈56.8 nV, the ADC ceiling is about 146 dB, and 2% accuracy is 34.0 dB.
ExplainAdding bits keeps lowering the rounding floor while the sensor's 2% bias line stays still.
Ideal ADC SNR
- reference noise
- Needs separate evidence
- effective-number-of-bits loss
- Needs separate evidence
- nonlinearity
- Needs separate evidence
- missing codes
- Needs separate evidence
- gain/offset error
- Needs separate evidence
- front-end noise
- Needs separate evidence
- bandwidth
- Needs separate evidence
- A 2% data-sheet value may itself depend on range, temperature, aging, calibration, and confidence convention
- Needs separate evidence
Use field evidence or a deeper model before release.
5. Work the 24-bit converter
6. Work the weakest-link gap
Those extra digits resolve the sensor's error more finely. They do not make the physical claim more accurate.
7. Check yourself
What does one extra ideal ADC bit do?
What is the 2% accuracy figure on this scale?
Can averaging remove a stable 2% bias?
These are the chapter inputs, worked results, and named teaching assumptions.
- 24-bit-versus-2% claim and labels 3.3 V as catalog-typical rather than chapter-specified
- Named teaching assumption
- Its worked values are 16,777,216 levels
- Sensor scale, pressure, or digital result
- 197 nV step
- Voltage or voltage-step value
- 56.8 nV RMS
- Voltage or voltage-step value
- 146 dB ADC ceiling
- Gain, loss, margin, or level ratio
- 34.0 dB accuracy scale
- Gain, loss, margin, or level ratio
- 112 dB gap
- Gain, loss, margin, or level ratio
- about 410,000×
- Percentage, ratio, or gain
Ideal quantisation arithmetic is not an end-to-end uncertainty budget.