Math Bridge: Resolution Versus Accuracy

A field team faces an unresolved physical question: Why 24 bits cannot rescue 2% accuracy They must answer it before changing adc resolution in bits on the real device. Predict the direction first.

See the relationship before changing it

Set the input, apply the rule, then read the result with its unit.

The retained audit below checks several chapter fixtures. This added model holds every other chapter fixture fixed, so the numeric fixture does not switch without explanation.

Derive the baseline in four named moves

1
Name the input. The chapter baseline for adc resolution in bits is 24.
2
Name the relationship. q=Vref/2^N; σq=q/√12; error ratio=20log10(1/ε)
3
Substitute the chapter fixture. Set adc resolution in bits to 24. The page ledger gives code step as 196.7 nV.
4
Read the result. Keep nV beside the value. Use it only inside the technical boundary on this page.

Predict, then change adc resolution in bits

Try Predict the direction of code step. Move one control, calculate, then check your prediction.

Observe Adding bits keeps lowering the rounding floor while the sensor's 2% bias line stays still. Reset the control to 24 and compare code step.

Explain Only adc resolution in bits moves here. The other chapter fixtures remain fixed.

Check yourself

What should you do before trusting a moved-control result?

Answer: Predict its direction, apply the shown relationship, keep the units, and reset to the worked baseline.

What does this small model leave out?

Answer: Only adc resolution in bits moves. Field effects named in the page's technical boundary stay fixed.

1. Name two different errors

Quantisation rounds voltage into one of 2^N bins. Accuracy says how far the sensor's calibrated response can sit from the physical reference.

Phoebe: A finer ruler gives more digits. It does not move a wrongly placed zero mark.

2. Derive the ADC floor

Count levelslevels=2^N.

Find one stepq=Vref/2^N.

Uniform RMSσq=q/√12 and SNRADC≈6.02N+1.76 dB.

3. Express sensor error as a separate ratio

For fractional accuracy ε, compare full scale with that error fraction.

Inverse error ratio=20 log10(1/ε)

The ADC sine-wave SNR and inverse full-scale sensor-error ratio describe different limits. Do not subtract them to estimate system SNR or accuracy.

4. Try the ADC bits

q=Vref/2^N; σq=q/√12; error ratio=20log10(1/ε)

TryAdd converter bits while keeping the chapter's 2% sensor accuracy fixed.

ObserveAt 24 bits, q≈197 nV, σq≈56.8 nV, the ADC ceiling is about 146 dB, and 2% accuracy is 34.0 dB.

ExplainAdding bits keeps lowering the rounding floor while the sensor's 2% bias line stays still.

Technical boundaries.

Ideal ADC SNR

reference noise: Needs separate evidence
effective-number-of-bits loss: Needs separate evidence
nonlinearity: Needs separate evidence
missing codes: Needs separate evidence
gain/offset error: Needs separate evidence
front-end noise: Needs separate evidence
bandwidth: Needs separate evidence
A 2% data-sheet value may itself depend on range, temperature, aging, calibration, and confidence convention: Needs separate evidence

Use field evidence or a deeper model before release.

5. Work the 24-bit converter

2^24=16,777,216 levels

q=3.3/16,777,216=197 nV; σq=56.8 nV

SNRADC=6.02×24+1.76≈146 dB

6. Compare unlike limits

inverse error ratio=20log10(1/0.02)=34.0 dB

146 dB is ideal sine-wave SNR; 34.0 dB is an inverse accuracy-error ratio. They cannot be subtracted as like-for-like limits.

The ADC SNR and inverse sensor-error ratio describe different quantities. More converter bits cannot remove a stable physical bias.

7. Check yourself

What does one extra ideal ADC bit do?

Answer: It halves the voltage step and improves the ideal quantisation ceiling by about 6 dB.

What is the inverse ratio of a 2% full-scale error?

Answer: 20log10(1/0.02)=34.0 dB.

Can averaging remove a stable 2% bias?

Answer: No. Averaging can reduce independent random scatter, but a systematic bias needs calibration or correction.

Honesty boundary.

These are the chapter inputs, worked results, and named teaching assumptions.

24-bit-versus-2% claim and labels 3.3 V as catalog-typical rather than chapter-specified: Named teaching assumption
Its worked values are 16,777,216 levels: Sensor scale, pressure, or digital result
197 nV step: Voltage or voltage-step value
56.8 nV RMS: Voltage or voltage-step value
146 dB ADC ceiling: Gain, loss, margin, or level ratio
34.0 dB inverse error ratio: Gain, loss, margin, or level ratio

Ideal quantisation arithmetic is not an end-to-end uncertainty budget.