Math Bridge: Switched Capacitance and DVFS

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Math BridgeEnergy & PowerStruggle-friendly runway

Why does lowering voltage save more than slowing the clock?

Read current per MHz as switched capacitance, then follow the squared voltage term in CV²f.

Battery Bruno, the energy and power guideBattery Bruno guides
The one targetTurn an MCU current-per-MHz line into a DVFS power decision.
The chapter case50 µA/MHz at 1.8 V and 48 MHz, reduced to 24 MHz.
What it buys youA quantitative split between clock-only and voltage-plus-clock savings.

A field team faces an unresolved physical question: Why does lowering voltage save more than slowing the clock? They must answer it before changing effective capacitance on the real device. Predict the direction first.

See the relationship before changing it

The figure reads from left to right. The blue card is effective capacitance. The middle card applies this page's relationship. The green card is full current. Walk the arrows once: set the input, apply the rule, then read the result with its unit.

The retained audit below checks several chapter fixtures. This added model holds every other chapter fixture fixed, so the numeric fixture does not switch without explanation.

Effective capacitance changes full current An input card leads through the page relationship to the full current result. SET INPUT ONE CONTROL APPLY RULE predict calculate check units READ RESULT
Walk the arrows. Halving frequency removes half the transitions. Lowering voltage also reduces both charge moved per transition and energy per unit charge.

Derive the baseline in four named moves

  1. 1

    Name the input. The chapter baseline for effective capacitance is 1.2.

  2. 2

    Name the relationship. C=(50x10⁻⁶/10⁶)/1.8=27.8 pF Ifull=50 uA/MHzx48 MHz=2.40 mA Pfull=2.40 mAx1.8 V=4.32 mW PDVFS=CV²f=0.960 mW at 1.2 V and 24 MHz

  3. 3

    Substitute the chapter fixture. Set effective capacitance to 1.2. The page ledger gives full current as 2.400 mA.

  4. 4

    Read the result. Keep mA beside the value. Use it only inside the technical boundary on this page.

Predict, then change effective capacitance

Try Predict the direction of full current. Move one control, calculate, then check your prediction.

1.2
Chapter baseline
Full current

Observe Halving frequency removes half the transitions. Lowering voltage also reduces both charge moved per transition and energy per unit charge. Reset the control to 1.2 and compare full current.

Explain Only effective capacitance moves here. The other chapter fixtures remain fixed.

Check yourself

What should you do before trusting a moved-control result?
Answer: Predict its direction, apply the shown relationship, keep the units, and reset to the worked baseline.
What does this small model leave out?
Answer: Only effective capacitance moves. Field effects named in the page's technical boundary stay fixed.

Honesty note. This teaching model changes only effective capacitance. It replays the chapter fixture; it is not a field prediction.

1. Start with the physical story

Every digital transition moves charge onto or off a real capacitance. More transitions per second use more power, and a higher rail moves more charge at more energy per transition. That is why frequency is linear but voltage is squared.

Battery Bruno: Clock gating removes selected transitions; it does not remove leakage or every asynchronous transition.

2. Name every algebra move

1

Read current per MHzConvert 50 µA/MHz into amperes per hertz.

2

Recover capacitanceUse I/f=CV, so C=(I/f)/V.

3

Find full currentMultiply current per MHz by 48 MHz.

4

Find full powerMultiply current by 1.8 V.

5

Scale frequencyUse CV²f at 24 MHz and the same rail.

6

Scale bothUse the reduced rail in the squared voltage term.

3. Reproduce the chapter case

C=(50×10⁻⁶/10⁶)/1.8=27.8 pF
Ifull=50 µA/MHz×48 MHz=2.40 mA
Pfull=2.40 mA×1.8 V=4.32 mW
PDVFS=CV²f=0.960 mW at 1.2 V and 24 MHz

Frequency-only scaling gives 2.16 mW and saves 50.0%. Adding the 1.2 V rail gives 0.960 mW and saves 77.8%.

4. Try one real input

TryLower the reduced rail and predict the curved, not linear, power response.

Effective capacitance
Full current
Full power
Frequency-only power
DVFS power
Frequency-only saving
DVFS saving

ObserveThe recovered capacitance and full-power case stay fixed. Reduced power bends with voltage squared; returning to 1.8 V collapses the result to the frequency-only case.

ExplainHalving frequency removes half the transitions. Lowering voltage also reduces both charge moved per transition and energy per unit charge.

Technical boundaries.

This is the dynamic switching term, not total MCU power.

Activity factor
The effective datasheet value already folds in a workload-specific switching pattern.
Leakage
Static power remains and may grow as a share at low frequency.
Timing
A device may not meet 24 MHz timing at every chosen voltage.

Correct, not complete: validate available voltage-frequency points and measured whole-chip power.

5. Use the result in the design

Choose a supported voltage-frequency pair, measure workload completion time, and compare total energy rather than dynamic power alone.

6. Record the evidence state

Keep silicon revision, rail, clock, workload, activity, runtime, current trace, temperature, and enabled peripherals.

7. Check yourself

Why is 50 µA/MHz related to capacitance?
Answer: Since P=IV and P=CV²f, dividing current by frequency gives CV.
Why is 24 MHz at 1.8 V exactly half the dynamic power?
Answer: Only f changed, and f appears linearly.
Does clock gating remove leakage?
Answer: No. Leakage is a separate static term.
Honesty boundary.

The arithmetic uses the chapter's catalog-typical 50 µA/MHz example.

Activity factor
The effective datasheet value already folds in a workload-specific switching pattern.
Leakage
Static power remains and may grow as a share at low frequency.
Timing
A device may not meet 24 MHz timing at every chosen voltage.

Correct, not complete: validate available voltage-frequency points and measured whole-chip power.

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