Math Bridge: PLC Current-Loop Signal Chain

A field team faces an unresolved physical question: How does 4–20 mA become a trustworthy 1 kHz sample? They must answer it before changing sample rate on the real device. Predict the direction first.

See the relationship before changing it

The figure reads from left to right. The blue card is sample rate. The middle card applies this page's relationship. The green card is sample period. Walk the arrows once: set the input, apply the rule, then read the result with its unit.

The retained audit below checks several chapter fixtures. This added model holds every other chapter fixture fixed, so the numeric fixture does not switch without explanation.

Walk the arrows. An anti-alias design starts from the wanted band, forbidden interferers, required attenuation, filter order, tolerances, and ADC sample behavior—not from fc<fN alone.

Derive the baseline in four named moves

1
Name the input. The chapter baseline for sample rate is 1000.
2
Name the relationship. Vlow=(0.004)(250)=1.00 V; Vhigh=(0.020)(250)=5.00 V fs=1000 Hz; Ts=1/1000=1.00 ms; fN=500 Hz C=1/[2π(1000)(400)]=397.9 nF τ=RC=0.3979 ms q=(5-1)/2¹²=0.9766 mV
3
Substitute the chapter fixture. Set sample rate to 1000. The page ledger gives sample period as 1.00 ms.
4
Read the result. Keep ms beside the value. Use it only inside the technical boundary on this page.

Predict, then change sample rate

Try Predict the direction of sample period. Move one control, calculate, then check your prediction.

Observe An anti-alias design starts from the wanted band, forbidden interferers, required attenuation, filter order, tolerances, and ADC sample behavior—not from fc<fN alone. Reset the control to 1000 and compare sample period.

Explain Only sample rate moves here. The other chapter fixtures remain fixed.

Check yourself

What should you do before trusting a moved-control result?

Answer: Predict its direction, apply the shown relationship, keep the units, and reset to the worked baseline.

What does this small model leave out?

Answer: Only sample rate moves. Field effects named in the page's technical boundary stay fixed.

1. Start with the physical story

A PLC cannot digitise current directly. A shunt resistor makes voltage, an analogue filter limits high-frequency energy, and a sample clock turns the filtered signal into discrete measurements. Each stage must agree on units and bandwidth.

Radio Remi: Nyquist is a boundary on the sampler, not a promise that the filter removed everything above it.

2. Name every algebra move

Convert currentMultiply 0.004 A and 0.020 A by 250 Ω.

Find spanSubtract 1.00 V from 5.00 V.

Convert periodInvert sample rate and multiply by 1,000 for milliseconds.

Set NyquistDivide sample rate by two.

Solve the capacitorRearrange fc=1/(2πRC) to C=1/(2πRfc).

Find ADC stepDivide the 4.00 V span by 2¹² codes.

3. Reproduce the chapter case

Vlow=(0.004)(250)=1.00 V; Vhigh=(0.020)(250)=5.00 V
fs=1000 Hz; Ts=1/1000=1.00 ms; fN=500 Hz
C=1/[2π(1000)(400)]=397.9 nF
τ=RC=0.3979 ms
q=(5−1)/2¹²=0.9766 mV

The 400 Hz pole is 80% of the 500 Hz Nyquist boundary. That reproduces the chapter's arithmetic, but a first-order pole there supplies little stopband attenuation and is not a validated anti-alias design.

4. Try one real input

TryMove sample rate and predict period, Nyquist, and the margin above the fixed 400 Hz pole.

ObserveRaising sample rate shortens period and raises Nyquist, so the fixed 400 Hz pole occupies a smaller share of the unique band. The voltage span and code step do not change.

ExplainAn anti-alias design starts from the wanted band, forbidden interferers, required attenuation, filter order, tolerances, and ADC sample behavior—not from fc<fN alone.

Technical boundaries.

This ledger models an ideal shunt, one ideal RC pole, uniform sampling, and an ideal 12-bit ADC.

Loop: Compliance voltage, burden, cable faults, isolation, tolerance, drift, and common-mode limits constrain the 4–20 mA input.
Filter: One pole at 400 Hz does not specify stopband attenuation near or above 500 Hz; a real design may need a lower cutoff or higher order.
ADC: Reference error, input settling, sample capacitor, INL, DNL, noise, and ENOB reduce ideal performance.

Correct, not complete: this calculation does not validate an anti-alias filter or a Level-1 control deadline.

5. Use the result in the design

Write the wanted signal band and worst unwanted frequency first. Choose filter order and cutoff from attenuation requirements, then sample fast enough for transition band, timing, and processing margin.

6. Record the evidence state

Keep loop range, shunt value and tolerance, compliance and isolation, filter topology and components, measured response, sample clock and jitter, ADC reference and ENOB, timestamps, missed deadlines, and calibration.

7. Check yourself

Why does 4 mA become 1.00 V?

Answer: Ohm's law gives 0.004 A × 250 Ω = 1.00 V.

Why is fc=400 Hz not enough to prove anti-alias safety?

Answer: Nyquist is 500 Hz, but a first-order filter at 400 Hz still passes substantial energy near and above that boundary.

Does a 0.977 mV ideal step equal real accuracy?

Answer: No. Reference, offset, gain, linearity, noise, settling, and calibration errors remain.

Honesty boundary.

The arithmetic reproduces the chapter's 4–20 mA, 250 Ω, 1 kHz, 400 Hz, and 12-bit example while correcting its safety wording.

Loop: Compliance voltage, burden, cable faults, isolation, tolerance, drift, and common-mode limits constrain the 4–20 mA input.
Filter: One pole at 400 Hz does not specify stopband attenuation near or above 500 Hz; a real design may need a lower cutoff or higher order.
ADC: Reference error, input settling, sample capacitor, INL, DNL, noise, and ENOB reduce ideal performance.

Correct, not complete: this calculation does not validate an anti-alias filter or a Level-1 control deadline.