Math Bridge: ADC Steps and Settling

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Math BridgeReference ArchitecturesStruggle-friendly runway

Can a 12-bit ADC still read the wrong voltage?

Yes. Count size, sample rate, and physical settling are three separate checks.

Phoebe, the physics guidePhoebe guides
The one targetProve the valve input is both precise enough and settled in time.
The chapter case12 bits, 3.3 V, 5.0 pF, 5.0 Hz, and 10–100 kΩ.
What it buys youAn ADC acquisition setting you can review.

A field team faces an unresolved physical question: Can a 12-bit ADC still read the wrong voltage? They must answer it before changing adc source resistance in kilohms on the real device. Predict the direction first.

See the relationship before changing it

The figure reads from left to right. The blue card is adc source resistance in kilohms. The middle card applies this page's relationship. The green card is code step. Walk the arrows once: set the input, apply the rule, then read the result with its unit.

The retained audit below checks several chapter fixtures. This added model holds every other chapter fixture fixed, so the numeric fixture does not switch without explanation.

ADC source resistance in kilohms changes code step An input card leads through the page relationship to the code step result. SET INPUT ONE CONTROL APPLY RULE predict calculate check units READ RESULT
Walk the arrows. Resistance changes the RC timing formula, not the converter's code count. More resolution cannot compensate for an unfinished charge.

Derive the baseline in four named moves

  1. 1

    Name the input. The chapter baseline for adc source resistance in kilohms is 100.

  2. 2

    Name the relationship. q=Vref/2^N; τ=RC; tsettle=(N+1)ln(2)τ; fs,min=2fmax

  3. 3

    Substitute the chapter fixture. Set adc source resistance in kilohms to 100. The page ledger gives code step as 0.806 mV.

  4. 4

    Read the result. Keep mV beside the value. Use it only inside the technical boundary on this page.

Predict, then change adc source resistance in kilohms

Try Predict the direction of code step. Move one control, calculate, then check your prediction.

100
Chapter baseline
Code step

Observe Resistance changes the RC timing formula, not the converter's code count. More resolution cannot compensate for an unfinished charge. Reset the control to 100 and compare code step.

Explain Only adc source resistance in kilohms moves here. The other chapter fixtures remain fixed.

Check yourself

What should you do before trusting a moved-control result?
Answer: Predict its direction, apply the shown relationship, keep the units, and reset to the worked baseline.
What does this small model leave out?
Answer: Only adc source resistance in kilohms moves. Field effects named in the page's technical boundary stay fixed.

Honesty note. This teaching model changes only adc source resistance in kilohms. It replays the chapter fixture; it is not a field prediction.

1. Start with three different questions

Bits set the size of one code. Sample rate decides which changes can be seen. Source resistance and the ADC capacitor decide whether the input voltage arrives before conversion starts.

Phoebe: A fine ruler gives a bad answer if you read it before the object stops moving.

2. Name the algebra moves

1

Count codeslevels = 2^N.

2

Divide the spanq = Vref/levels.

3

Double the bandwidthfs,min = 2fmax.

4

Form the time constantτ = RsourceCs/h.

5

Allow half an LSBtsettle ≈ (N+1)ln(2)τ.

3. Work the two source resistances

q=3.3/4096=0.806 mV; SNR=6.02(12)+1.76=74.0 dB

A 5.0 Hz input needs at least 10.0 Hz sampling; the chapter's practical 10× schedule is 50.0 Hz. With 5.0 pF, 10 kΩ gives τ=50.0 ns and 0.451 µs settling. At 100 kΩ those become 500 ns and 4.51 µs.

4. Try one controlled change

q=Vref/2^N; τ=RC; tsettle=(N+1)ln(2)τ; fs,min=2fmax

TryMove only the source resistance. Bit count, reference, capacitor, and signal bandwidth stay fixed.

Code levels
Code step
Noise power
Ideal SNR
Nyquist minimum
Practical schedule
RC time constant
Half-LSB settling

ObserveAt 100 kΩ, the code step remains 0.806 mV and SNR remains 74.0 dB, but settling grows to 4.51 µs.

ExplainResistance changes the RC timing formula, not the converter's code count. More resolution cannot compensate for an unfinished charge.

Technical boundaries.

These are ideal quantisation and first-order RC checks.

ADC
Offset, gain error, nonlinearity, noise, reference drift, and multiplexing remain
Filter
A real anti-alias filter needs attenuation, not only a Nyquist number
Source
Switch resistance, leakage, protection parts, and driver recovery remain

Use the MCU datasheet's acquisition model and measure the protected input at temperature.

5. Keep units visible

Convert kilohms to ohms and picofarads to farads before multiplying. Their product is seconds. Multiplying by 10^6 then gives microseconds.

6. Carry the evidence

Record ADC mode, Vref, bits, source network, sample capacitor, acquisition cycles, clock, signal bandwidth, filter response, channel switching, temperature, and measured settling error.

7. Check yourself

Why does 12 bits mean 4096 levels?
Answer: Each bit doubles the choices, so twelve bits give 2^12.
Why is 10 Hz only the minimum for a 5 Hz signal?
Answer: Nyquist prevents ideal alias overlap; a real filter needs extra transition room.
What happens when source resistance rises tenfold?
Answer: Both τ and the required settling time rise tenfold.
Honesty boundary.

The page joins three necessary checks; it does not certify an ADC channel.

0.806 mV
Ideal code step
10.0 Hz
Nyquist minimum for 5.0 Hz
4.51 µs
Ideal 100 kΩ first-order settling

Go deeper in the chapter and validate the exact MCU, source, filter, and timing sequence.

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