Phoebe guidesA field team faces an unresolved physical question: Can a 12-bit ADC still read the wrong voltage? They must answer it before changing adc source resistance in kilohms on the real device. Predict the direction first.
See the relationship before changing it
Set the input, apply the rule, then read the result with its unit.
The retained audit below checks several chapter fixtures. This added model holds every other chapter fixture fixed, so the numeric fixture does not switch without explanation.
Derive the baseline in four named moves
- 1
Name the input. The chapter baseline for adc source resistance in kilohms is 100.
- 2
Name the relationship. q=Vref/2^N; τ=RC; tsettle=(N+1)ln(2)τ; fs,min=2fmax
- 3
Substitute the chapter fixture. Set adc source resistance in kilohms to 100. The page ledger gives rc time constant as 500 ns.
- 4
Read the result. Keep ns beside the value. Use it only inside the technical boundary on this page.
Predict, then change adc source resistance in kilohms
Try Predict the direction of rc time constant. Move one control, calculate, then check your prediction.
Observe Predict an increase in rc time constant as the input increases over this range. Reset to the chapter baseline and compare.
Explain Only adc source resistance in kilohms moves here. The other chapter fixtures remain fixed.
Source: content/reference-architectures/hardware-power-interfaces-decision-route.qmd — Phoebe's Field Notes: Why "The Reference And Divider Settle" Is A Real Deadline. Use the chapter equation and fixed ledger above; only the named input varies.
Check yourself
What should you do before trusting a moved-control result?
What does this small model leave out?
1. Start with three different questions
Bits set the size of one code. Sample rate decides which changes can be seen. Source resistance and the ADC capacitor decide whether the input voltage arrives before conversion starts.
2. Name the algebra moves
Count codeslevels = 2^N.
Divide the spanq = Vref/levels.
Double the bandwidthfs,min = 2fmax.
Form the time constantτ = RsourceCs/h.
Allow half an LSBtsettle ≈ (N+1)ln(2)τ.
3. Work the two source resistances
A 5.0 Hz input needs at least 10.0 Hz sampling; the chapter's practical 10× schedule is 50.0 Hz. With 5.0 pF, 10 kΩ gives τ=50.0 ns and 0.451 µs settling. At 100 kΩ those become 500 ns and 4.51 µs.
4. Try one controlled change
TryMove only the source resistance. Bit count, reference, capacitor, and signal bandwidth stay fixed.
ObserveAt 100 kΩ, the code step remains 0.806 mV and SNR remains 74.0 dB, but settling grows to 4.51 µs.
ExplainResistance changes the RC timing formula, not the converter's code count. More resolution cannot compensate for an unfinished charge.
These are ideal quantisation and first-order RC checks.
- ADC
- Offset, gain error, nonlinearity, noise, reference drift, and multiplexing remain
- Filter
- A real anti-alias filter needs attenuation, not only a Nyquist number
- Source
- Switch resistance, leakage, protection parts, and driver recovery remain
Use the MCU datasheet's acquisition model and measure the protected input at temperature.
5. Keep units visible
Convert kilohms to ohms and picofarads to farads before multiplying. Their product is seconds. Multiplying by 10^6 then gives microseconds.
6. Carry the evidence
Record ADC mode, Vref, bits, source network, sample capacitor, acquisition cycles, clock, signal bandwidth, filter response, channel switching, temperature, and measured settling error.
7. Check yourself
Why does 12 bits mean 4096 levels?
Why is 10 Hz only the minimum for a 5 Hz signal?
What happens when source resistance rises tenfold?
The page joins three necessary checks; it does not certify an ADC channel.
- 0.806 mV
- Ideal code step
- 10.0 Hz
- Nyquist minimum for 5.0 Hz
- 4.51 µs
- Ideal 100 kΩ first-order settling
Go deeper in the chapter and validate the exact MCU, source, filter, and timing sequence.