Math Bridge: Pull Resistor Sizing

A field team faces an unresolved physical question: How strong should a pull resistor be? They must answer it before changing pull resistance on the real device. Predict the direction first.

See the relationship before changing it

The figure reads from left to right. The blue card is pull resistance. The middle card applies this page's relationship. The green card is leakage error. Walk the arrows once: set the input, apply the rule, then read the result with its unit.

The retained audit below checks several chapter fixtures. This added model holds every other chapter fixture fixed, so the numeric fixture does not switch without explanation.

Walk the arrows. The same resistance sits in three different equations, so saving current cannot be judged without the leakage and timing contracts.

Derive the baseline in four named moves

1
Name the input. The chapter baseline for pull resistance is 10.
2
Name the relationship. Verror=(1 uA)(10 kohm)=10.0 mV τ=(10 kohm)(5 pF)=50.0 ns t90=2.303τ=115 ns Iactive=3.30 V/10 kohm=0.330 mA margin used=10 mV/(0.3x3.30 V)=1.01%
3
Substitute the chapter fixture. Set pull resistance to 10. The page ledger gives leakage error as 10.0 mV.
4
Read the result. Keep mV beside the value. Use it only inside the technical boundary on this page.

Predict, then change pull resistance

Try Predict the direction of leakage error. Move one control, calculate, then check your prediction.

Observe The same resistance sits in three different equations, so saving current cannot be judged without the leakage and timing contracts. Reset the control to 10 and compare leakage error.

Explain Only pull resistance moves here. The other chapter fixtures remain fixed.

Check yourself

What should you do before trusting a moved-control result?

Answer: Predict its direction, apply the shown relationship, keep the units, and reset to the worked baseline.

What does this small model leave out?

Answer: Only pull resistance moves. Field effects named in the page's technical boundary stay fixed.

1. Start with the physical story

A floating CMOS gate is mostly a tiny capacitor. Leakage can keep charging it because no resistor returns it to a rail. A pull resistor supplies that return path, but a larger value also turns more leakage into voltage error and slows the RC edge.

Eddie: A weak pull saves active current; a strong pull buys noise and timing margin. The design is a balance, not a magic 10 kΩ rule.

2. Name every algebra move

Convert resistanceTurn kilohms into ohms.

Price leakageUse Verror=IleakRpull.

Price speedUse τ=RpullC and t90=−ln(0.1)τ.

Price active currentUse Iactive=Vrail/Rpull.

Compare with thresholdDivide leakage error by the guaranteed LOW limit.

3. Reproduce the chapter case

Verror=(1 µA)(10 kΩ)=10.0 mV
τ=(10 kΩ)(5 pF)=50.0 ns
t90=2.303τ=115 ns
Iactive=3.30 V/10 kΩ=0.330 mA
margin used=10 mV/(0.3×3.30 V)=1.01%

The familiar 10 kΩ choice is not just a convention: it makes all three costs visible and leaves 980 mV of this illustrative LOW-threshold margin.

4. Try one real input

TryMove pull resistance and predict which cost rises and which falls.

ObserveIncreasing R reduces active current, but leakage error and both edge times grow in direct proportion.

ExplainThe same resistance sits in three different equations, so saving current cannot be judged without the leakage and timing contracts.

Technical boundaries.

This is a first-order lumped input model with fixed worst-case leakage and capacitance.

Thresholds: Use guaranteed VIH/VIL values from both connected devices, not a generic 0.3VDD rule.
Leakage: Temperature, contamination, protection networks, and connected drivers can raise it.
Edges: Trace capacitance, switch bounce, EMI, and protocol timing add constraints.

Correct, not complete: this ledger does not qualify a GPIO, board, button, or open-drain bus.

5. Use the result in the design

Set the allowable idle-voltage error and edge deadline first, find the largest resistance that meets both, then confirm the active driver can sink or source its current.

6. Record the evidence state

Record rail voltage, resistor tolerance, worst-case leakage, total capacitance, guaranteed thresholds, required settle time, active current, temperature, and measured idle/edge voltages.

7. Check yourself

Why does a larger pull increase leakage error?

Answer: The same leakage current produces more voltage across a larger resistance: V=IR.

Why does a smaller pull cost more energy when asserted?

Answer: The driver must oppose Vrail/Rpull, which rises as resistance falls.

Does 10 kΩ certify every button input?

Answer: No. Real leakage, capacitance, thresholds, bounce, EMI, tolerance, and temperature must be checked.

Honesty boundary.

The arithmetic reproduces the chapter's 1 µA, 5 pF, 3.30 V, and 10 kΩ illustration.

Thresholds: Use guaranteed VIH/VIL values from both connected devices, not a generic 0.3VDD rule.
Leakage: Temperature, contamination, protection networks, and connected drivers can raise it.
Edges: Trace capacitance, switch bounce, EMI, and protocol timing add constraints.

Correct, not complete: this ledger does not qualify a GPIO, board, button, or open-drain bus.