13 Floating Input and Pull Resistor Contracts
13.1 Start Simple
Imagine a button input that randomly changes state when no one touches it. The pin is not making a decision; it is floating because nothing defines the idle voltage strongly enough. Start by choosing the default state, the pull resistor value, and the leakage or edge-speed evidence that proves the input will stay there.
13.2 Learning Objectives
After this page, you should be able to:
- Explain why high-impedance CMOS inputs become undefined when left floating.
- Choose pull-up or pull-down resistors to give logic inputs a safe default state.
- Balance pull-resistor strength against current draw, edge speed, leakage, and noise immunity.
- Diagnose floating-input symptoms such as random logic readings, oscillation, and excess current.
- Explain how mid-level CMOS inputs create shoot-through current and how pulls stop it.
13.3 Why Materials Come First
Conductors, Insulators, and Semiconductors introduces charge flow, insulation, semiconductor control, and the passive/active component families used in IoT circuits. This page turns one material fact into a board-level contract: insulated CMOS gates draw almost no input current, so they also need an explicit path to a known voltage whenever the node would otherwise float.
Use it when a button input reads randomly, an unused MCU pin changes state by itself, a shared line needs an idle level, a board draws unexpected sleep current, or a pull resistor must be sized from current, capacitance, leakage, and noise constraints.
Phoebe’s Why
A CMOS gate’s input impedance is gigaohms – for circuit-analysis purposes, an open circuit. With nothing else connected, the node has no finite-resistance path to any reference voltage, so even a nanoamp-scale stray current (input bias leakage, board contamination, a nearby switching trace) has nowhere to flow except onto the node’s own tiny parasitic capacitance. A current with no bleed path just charges a capacitor: \(I = C\,dV/dt\) with no opposing term, so the voltage is free to drift anywhere, including the mid-supply region where this chapter’s own text notes both halves of the CMOS input pair conduct at once. Add a pull resistor and everything changes: now there is a finite path to a known rail, so the node has an equilibrium voltage instead of an open-ended drift. The same resistor also happens to set how fast the node’s own capacitance charges through it – which is why one component value has to answer two different physics questions at once, and why this chapter’s strong-versus-weak table has entries in both the current column and the speed column.
The Derivation
Any leakage current forced through the pull resistor shows up as a plain Ohm’s-law offset from the intended rail:
\[V_{error} = I_{leak}\,R_{pull}\]
The same resistor, against the node’s parasitic capacitance \(C\), forms a first-order RC charging path:
\[V(t) = V_{rail}\left(1 - e^{-t/\tau}\right), \qquad \tau = R_{pull}\,C\]
Active current while a switch or driver pulls the node the other way is the same Ohm’s law relation the chapter already uses:
\[I_{active} = \frac{V_{rail}}{R_{pull}}\]
Worked Numbers: This Chapter’s Own Strong / Button / Weak Values
Using a catalog-typical CMOS logic input leakage of \(I_{leak} \approx 1\ \mu\text{A}\) (max) and a catalog-typical gate-plus-trace input capacitance \(C \approx 5\) pF, applied to this chapter’s own three named resistor values on its own \(3.30\) V rail:
| Pull value (this chapter’s own) | Leakage error \(I_{leak}R_{pull}\) | RC edge \(\tau=R_{pull}C\) | Active current \(V/R_{pull}\) |
|---|---|---|---|
| \(1\ \text{k}\Omega\) (strong) | \(1.00\) mV | \(5.00\) ns | \(3.30\) mA |
| \(10\ \text{k}\Omega\) (button example) | \(10.0\) mV | \(50.0\) ns | \(0.330\) mA |
| \(100\ \text{k}\Omega\) (weak) | \(100\) mV | \(500\) ns | \(0.033\) mA |
The middle row cross-checks the chapter’s own worked button example exactly: \(3.30/10{,}000 = 0.330\) mA. It also shows why \(10\ \text{k}\Omega\) is a comfortable default: its \(10.0\) mV leakage error is about \(1.01\%\) of a \(0.990\) V CMOS \(V_{IL}\) margin (\(0.3\times3.30\) V), while the \(100\ \text{k}\Omega\) weak pull already spends \(10.1\%\) of that same margin on leakage alone – a hundred-fold resistance increase does not cost a hundred-fold logic risk, but it is not free either, and the RC column shows the edge slowing by the same hundred-fold factor.
Overview: A Floating Input Is an Undefined Node
The gate of a CMOS logic input sits behind a thin insulating oxide, so the input is enormously high impedance — it senses voltage but draws almost no current (gigaohms, mostly capacitance). That is wonderful for not loading a signal, but it has a sharp edge: if you leave the input unconnected (floating), nothing defines its voltage. Stray charge, coupled noise, and nearby switching set it at random, so it can read HIGH and LOW unpredictably and even oscillate.
A pull-up resistor (to the supply) or pull-down resistor (to ground) gives the node a defined default level while remaining weak enough that an active driver can still override it. It is the bridge between "insulated, undefined" and "conductively tied to a known level."
Think of the pull resistor as a contract for every moment when no active circuit is driving the node. A push button is open most of the time, an unused MCU pin may never be driven, and an open-drain bus releases the wire between pulses. In all three cases the input needs a quiet answer before the real event arrives: idle HIGH, idle LOW, or whatever the protocol calls inactive. Without that answer, the node is an antenna and a tiny capacitor, not a logic signal.
High-Z input
Behind an insulating gate oxide: senses voltage, draws almost no current.
Floating = undefined
Unconnected, noise sets the level; the input reads randomly and may oscillate.
Pull-up
Weak resistor to Vcc — default HIGH until something pulls it LOW.
Pull-down
Weak resistor to GND — default LOW until something drives it HIGH.
The direction is a design choice, not a magic property of the input. Choose a pull-up when the normal inactive state should read HIGH, such as a button that shorts the pin to ground when pressed. Choose a pull-down when the normal inactive state should read LOW, such as a jumper or sensor output that drives HIGH only when present. Then verify the active driver can comfortably sink or source the pull current when it asserts the opposite state.
Overview Knowledge Check
Practitioner: Sizing a Pull Resistor
Pull-resistor value is a balance. Too strong (small resistance) wastes current whenever a driver pulls the opposite way — a continuous I = Vcc / R flows — and can exceed what a driver is rated to sink. Too weak (large resistance) means the pull current is tiny, so the node charges its own capacitance slowly (giving soft, slow edges) and is more easily disturbed by leakage and noise.
Start from the two worst cases. In the active state, calculate the current through the pull and compare it with the switch contact, transistor, or GPIO sink/source rating. In the idle state, compare the pull current with all leakage paths that can pull the node the wrong way: input leakage, board contamination, cable leakage, ESD devices, or an unpowered peripheral. A pull that is only a few times larger than the leakage uncertainty may pass in the lab and fail in humidity, heat, or sleep mode.
| Pull resistor | Good | Bad |
|---|---|---|
| Strong (e.g., 1 kΩ) | Fast edges, noise-robust, firm level | More current wasted when driven the other way (Vcc/R); heavier sink load |
| Weak (e.g., 100 kΩ) | Very low current | Slow rise/fall through node capacitance; more sensitive to leakage and noise |
Worked example — a button with a pull-up. A push button connects a 3.3 V input to ground when pressed, with a 10 kΩ pull-up to 3.3 V. Idle (button open): the pull-up holds the input at 3.3 V (HIGH) and draws essentially no current. Pressed: the button ties the node to ground (LOW) and the pull-up now passes 3.3 V / 10 kΩ = 0.33 mA to ground — small and harmless. Many microcontrollers offer configurable internal pull-ups (typically tens of kΩ) that remove the external part for exactly this job.
Now check speed. The pull resistor and the node capacitance make a simple RC edge: a larger resistor or longer cable charges more slowly. For a human button, even a slow microsecond-scale edge is usually fine because software debouncing dominates. For a shared open-drain interrupt, reset, or low-speed bus, the release edge may be part of a timing budget, so the pull must be strong enough to reach a valid logic threshold before the next sample. If low sleep current matters, document why an internal weak pull is acceptable or why the stronger external pull is worth the current.
Practitioner Knowledge Check
Under the Hood: Why a Floating CMOS Input Runs Hot
A CMOS input stage drives a complementary pair: a p-channel transistor to the supply and an n-channel to ground. At a clean HIGH or LOW, exactly one is fully on and the other fully off, so no current flows straight through. But a floating input can drift to a mid-level voltage, where both transistors are partly on at once, opening a conducting path from supply to ground through the pair. That shoot-through current wastes power and heats the chip, on top of leaving the logic state indeterminate. Tying the input to a defined level with a pull resistor turns one transistor fully off and closes that path — the concrete reason datasheets insist unused CMOS inputs must never be left floating.
The mid-level problem is separate from ordinary input leakage. Leakage is tiny current into or out of the input pin; shoot-through is current inside the input buffer after the floating voltage lands between the LOW and HIGH thresholds. A meter may show the external pin is not connected to anything, but the silicon still sees a voltage that asks both devices to conduct. The symptom can be random interrupts, high sleep current, EMI sensitivity, or a board that behaves differently when a hand, cable, or oscilloscope probe is nearby.
The same high-impedance idea reappears as a deliberate third state: a tri-state or open-drain output can be released to high-impedance so several devices can share one wire. A shared line like that also needs a pull resistor to define its idle level whenever every driver has let go — the same defined-vs-floating principle, now on the output side.
Open-drain buses make the sizing trade visible. Any device can pull the line LOW strongly, but the pull-up is the only thing that returns the line HIGH after release. Too weak a pull-up gives slow rising edges and late HIGH recognition; too strong a pull-up makes every LOW bit burn more current and may exceed a small device's sink-current limit. Schmitt-trigger inputs can add hysteresis so slow or noisy edges do not chatter, but they do not replace the pull. They still need the node to be biased toward a real idle level.