Math Bridge: Filtered PWM Ripple

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Math BridgeElectronicsStruggle-friendly runway

How much ripple survives a filtered PWM output?

Connect PWM duty cycle to average voltage, RC ripple, settling time, and DAC step scale.

Eddie, the electronics guideEddie guides
The one targetPredict average voltage and first-order ripple from duty and RC.
The chapter case3.3 V, 20 kHz, 10 kohm, 0.22 microfarad, and code 200 of 255.
What it buys youA quantitative choice between filtered PWM and a true DAC.

A technician must decide whether average output voltage is safe before changing eight-bit pwm code on the real device. The result is unresolved until the rule and units are checked. Predict the direction first.

See the relationship before changing it

The figure reads from left to right. The blue card is eight-bit pwm code. The middle card applies this page's rule. The green card is average output voltage. Walk the arrows once: set the input, apply the rule, then read the result with its unit.

The retained audit below checks several chapter fixtures. This model keeps those stated values fixed and changes only eight-bit pwm code, so the numeric fixture does not switch without explanation.

Eight-bit PWM code changes average output voltage An input card leads through the rule average = 3.3 V x code / 255 to the average output voltage result. INPUT PAGE INPUT APPLY THE RULE predict calculate check units OUTPUT RESULT
Walk the arrows. A larger PWM code raises average voltage before the filter smooths it.

Derive the baseline in four named moves

  1. 1

    Name the input. The chapter baseline is 200 counts.

  2. 2

    Name the relationship. average = 3.3 V x code / 255

  3. 3

    Substitute with units. 3.3 x 200 / 255 = 2.588 V

  4. 4

    Read the result. Keep the unit beside the value. Use it only inside the technical boundary on this page.

Predict, then change eight-bit pwm code

Try Predict the direction of average = 3.3 V x code / 255. Test another eight-bit pwm code, then compare average output voltage.

200 counts
Chapter baseline
Average output voltage

Observe A larger PWM code raises average voltage before the filter smooths it. Reset eight-bit pwm code to 200 and compare average output voltage.

Explain A larger PWM code raises average voltage before the filter smooths it.

Check yourself

What should you do before trusting a moved-control result?
Answer: Predict its direction, apply the shown relationship, keep the units, and reset to the worked baseline.
What does this small model leave out?
Answer: Only eight-bit pwm code moves here. Field effects named in the technical boundary stay fixed.

Honesty note. This teaching model changes only eight-bit pwm code. It is not a field prediction.

1. Start with the physical story

A slow RC cannot follow each pulse. It charges during on-time and discharges during off-time, leaving an average plus a repeating ripple.

Eddie: Fifty percent duty gives both phases the most balanced time, so D(1−D) makes its ripple the worst case.

2. Name every algebra move

1

Convert dutyD=duty percent/100.

2

Find averageVavg=DVs.

3

Build the time constanttau=RC.

4

Count periods per taufpwm×tau.

5

Estimate rippledeltaV=VsD(1−D)/(fpwmRC).

3. Reproduce the chapter case

D=200/255=0.7843
Vavg=3.3D=2.588 V
tau=(10 kohm)(0.22 microfarad)=2.20 ms
fpwm tau=44 periods
ripple=12.70 mV peak-to-peak
12-bit DAC step=0.806 mV

The filtered PWM ripple spans about sixteen 12-bit DAC steps even before load and component tolerances.

4. Try one real input

TryMove the control, predict the direction, then compare every output.

Duty
Average voltage
On time
Off time
RC time constant
Periods per RC
Ripple
12-bit DAC step
Ripple/DAC steps
Worst ripple

ObserveMoving toward 50% raises D(1−D) and ripple; moving duty upward also raises average voltage while shortening off-time.

ExplainAverage and ripple share duty but answer different questions. A correct set point can still be too noisy for the load.

Technical boundaries.

This is a transparent first-order teaching ledger tied to the chapter constants.

Approximation
The linear-ramp ripple formula assumes RC is much longer than one PWM period.
Load
Output loading changes the effective resistance, average, ripple, and settling.
Hardware
Timer jitter, switch resistance, capacitor ESR, and tolerance are omitted.

Correct, not complete: this ledger does not qualify a PWM pin, filter, load, DAC, or control loop.

5. Use the result in the design

Set allowed ripple and settling first, include the real load, then verify the exact waveform or choose a DAC when quiet output matters.

6. Record the evidence state

Record PWM clock, duty resolution, rail, R and C tolerances, load impedance, measured ripple, settling, temperature, and update rate.

7. Check yourself

Why is ripple worst near 50%?
Answer: The product D(1−D) peaks at one quarter when both charge and discharge phases are substantial.
Does the RC output become a true DAC?
Answer: No. It remains a filtered pulse train with ripple, settling, loading, and timer constraints.
Can a larger capacitor always fix ripple?
Answer: It reduces ripple but slows settling and may burden the driver or control loop.
Honesty boundary.

The arithmetic reproduces the named chapter case; it is an inspectable model, not a component approval.

Approximation
The linear-ramp ripple formula assumes RC is much longer than one PWM period.
Load
Output loading changes the effective resistance, average, ripple, and settling.
Hardware
Timer jitter, switch resistance, capacitor ESR, and tolerance are omitted.

Correct, not complete: this ledger does not qualify a PWM pin, filter, load, DAC, or control loop.

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