Math Bridge: ADC Sampling and Quantisation

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Math BridgeElectronicsStruggle-friendly runway

Where does an ADC lose time and amplitude detail?

Separate the sample-clock limit from the voltage-bin limit.

Eddie, the electronics guideEddie guides
The one targetKeep sampling and quantisation budgets separate and visible.
The chapter case5 kHz vibration, 12.5 kHz sampling, 12 bits, 3.3 V, and 40 mV/g.
What it buys youA channel specification that checks both bandwidth and ideal resolution.

A technician must decide whether nyquist frequency is safe before changing adc sample rate on the real device. The result is unresolved until the rule and units are checked. Predict the direction first.

See the relationship before changing it

The figure reads from left to right. The blue card is adc sample rate. The middle card applies this page's rule. The green card is nyquist frequency. Walk the arrows once: set the input, apply the rule, then read the result with its unit.

The retained audit below checks several chapter fixtures. This model keeps those stated values fixed and changes only adc sample rate, so the numeric fixture does not switch without explanation.

ADC sample rate changes nyquist frequency An input card leads through the rule ADC Nyquist = sample rate / 2 to the nyquist frequency result. INPUT PAGE INPUT APPLY THE RULE predict calculate check units OUTPUT RESULT
Walk the arrows. A faster sample clock raises the highest directly representable frequency.

Derive the baseline in four named moves

  1. 1

    Name the input. The chapter baseline is 12.5 kHz.

  2. 2

    Name the relationship. ADC Nyquist = sample rate / 2

  3. 3

    Substitute with units. 12.5 / 2 = 6.25 kHz

  4. 4

    Read the result. Keep the unit beside the value. Use it only inside the technical boundary on this page.

Predict, then change adc sample rate

Try Predict the direction of ADC Nyquist = sample rate / 2. Test another adc sample rate, then compare nyquist frequency.

12.5 kHz
Chapter baseline
Nyquist frequency

Observe A faster sample clock raises the highest directly representable frequency. Reset adc sample rate to 12.5 and compare nyquist frequency.

Explain A faster sample clock raises the highest directly representable frequency.

Check yourself

What should you do before trusting a moved-control result?
Answer: Predict its direction, apply the shown relationship, keep the units, and reset to the worked baseline.
What does this small model leave out?
Answer: Only adc sample rate moves here. Field effects named in the technical boundary stay fixed.

Honesty note. This teaching model changes only adc sample rate. It is not a field prediction.

1. Start with the physical story

The sample clock keeps only snapshots in time. The ADC code keeps only a voltage bin. Sampling too slowly folds frequencies; too few bits hide small amplitude changes. More bits cannot undo aliasing, and a faster clock cannot shrink an ADC bin.

Eddie: Ask two questions: can the clock distinguish the fastest motion, and can the code distinguish the smallest voltage change?

2. Name every algebra move

1

Find sample periodInvert the selected sample rate.

2

Find NyquistDivide sample rate by two.

3

Count samples per cycleDivide sample rate by 5 kHz.

4

Find one ADC binDivide 3.3 V by 2¹².

5

Translate ideal noiseUse q/√12, then divide by 40 mV/g.

3. Reproduce the chapter case

Ts=1/12.5 kHz=80.0 µs
fNyquist=12.5/2=6.25 kHz
samples/cycle=12.5/5=2.50
q=3.3/4096=0.806 mV
σq=q/√12=0.233 mV=0.00582 g

The clock clears the theoretical 10 kHz minimum by 2.5 kHz. The ideal half-bin amplitude uncertainty is 0.0101 g before any real sensor or reference error.

4. Try one real input

TryMove sample rate and predict which results change and which stay fixed.

Sample rate
Sample period
Nyquist boundary
Samples per 5 kHz cycle
Nyquist margin
ADC bin
Ideal noise
Ideal noise at sensor
Half-bin limit
Ideal SNR

ObserveThe clock-derived period, Nyquist, samples-per-cycle, and margin move. The bit-derived bin, noise, and ideal SNR do not.

ExplainRate controls time resolution; bits and reference span control amplitude resolution. They are independent design axes.

Technical boundaries.

This ideal ledger assumes a perfectly band-limited input, uniform quantisation error, and a noiseless reference.

Front end
The analogue anti-alias filter must attenuate content before the ADC samples it.
ADC
ENOB, aperture jitter, nonlinearity, reference noise, and input settling reduce performance.
Sensor
Sensitivity, bandwidth, offset, and its own noise must be measured.

Correct, not complete: this ledger does not validate a vibration channel or anti-alias filter.

5. Use the result in the design

Choose an analogue cutoff and stopband attenuation first, then sample above the usable band with implementation margin and choose ADC span/bits from the smallest required signal.

6. Record the evidence state

Record signal band, filter response, sample-clock accuracy and jitter, ADC reference and ENOB, sensor sensitivity/noise, input settling, measured spectrum, and calibration conditions.

7. Check yourself

Why is 12.5 kHz above the theoretical minimum?
Answer: A 5 kHz limit needs at least 10 kHz by Nyquist; 12.5 kHz adds 2.5 kHz of ideal boundary margin.
Does raising sample rate shrink a 12-bit ADC bin?
Answer: No. Bin width is Vref/2ᴺ and does not depend on the clock rate.
Does 74 dB certify the real channel SNR?
Answer: No. It is the ideal quantisation limit and omits sensor, reference, front-end, jitter, and ADC errors.
Honesty boundary.

The arithmetic reproduces the chapter's 5 kHz, 12.5 kHz, 12-bit, 3.3 V, and 40 mV/g illustration.

Front end
The analogue anti-alias filter must attenuate content before the ADC samples it.
ADC
ENOB, aperture jitter, nonlinearity, reference noise, and input settling reduce performance.
Sensor
Sensitivity, bandwidth, offset, and its own noise must be measured.

Correct, not complete: this ledger does not validate a vibration channel or anti-alias filter.

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