Math Bridge: Minimum ADC Bit Depth

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Math BridgeElectronicsStruggle-friendly runway

How many ADC bits does the signal really need?

Turn signal span and required percentage change into a range-aware ADC bit budget.

Eddie, the electronics guideEddie guides
The one targetCompute minimum bits from span and smallest meaningful change.
The chapter caseA 50 mV signal resolved to 1%, either conditioned to full span or left on 5 V.
What it buys youA bit budget that exposes wasted input range.

A technician must decide whether allowed voltage step is safe before changing allowed signal error on the real device. The result is unresolved until the rule and units are checked. Predict the direction first.

See the relationship before changing it

The figure reads from left to right. The blue card is allowed signal error. The middle card applies this page's rule. The green card is allowed voltage step. Walk the arrows once: set the input, apply the rule, then read the result with its unit.

The retained audit below checks several chapter fixtures. This model keeps those stated values fixed and changes only allowed signal error, so the numeric fixture does not switch without explanation.

Allowed signal error changes allowed voltage step An input card leads through the rule step = 50 mV x allowed percent / 100 to the allowed voltage step result. INPUT PAGE INPUT APPLY THE RULE predict calculate check units OUTPUT RESULT
Walk the arrows. Relaxing the percentage target permits a larger voltage step.

Derive the baseline in four named moves

  1. 1

    Name the input. The chapter baseline is 1 %.

  2. 2

    Name the relationship. step = 50 mV x allowed percent / 100

  3. 3

    Substitute with units. 50 mV x 1 / 100 = 0.50 mV

  4. 4

    Read the result. Keep the unit beside the value. Use it only inside the technical boundary on this page.

Predict, then change allowed signal error

Try Predict the direction of step = 50 mV x allowed percent / 100. Test another allowed signal error, then compare allowed voltage step.

1 %
Chapter baseline
Allowed voltage step

Observe Relaxing the percentage target permits a larger voltage step. Reset allowed signal error to 1 and compare allowed voltage step.

Explain Relaxing the percentage target permits a larger voltage step.

Check yourself

What should you do before trusting a moved-control result?
Answer: Predict its direction, apply the shown relationship, keep the units, and reset to the worked baseline.
What does this small model leave out?
Answer: Only allowed signal error moves here. Field effects named in the technical boundary stay fixed.

Honesty note. This teaching model changes only allowed signal error. It is not a field prediction.

1. Start with the physical story

Each bit halves a range. A base-2 logarithm simply counts how many halvings are needed before one code is smaller than the change you care about.

Eddie: Bits assigned to voltage the sensor never uses are empty precision.

2. Name every algebra move

1

Name the target gapdelta=signal span×precision percent.

2

Count required levelslevels=span/delta.

3

Take log base twoexact bits=log2(levels).

4

Round upwardNmin=ceil(exact bits).

5

Repeat for bare ADC spanUse the whole 5 V range if no gain stage exists.

3. Reproduce the chapter case

delta=50 mV×1%=0.5 mV
conditioned levels=50/0.5=100
conditioned bits=ceil(log2 100)=7
bare levels=5000/0.5=10000
bare bits=ceil(log2 10000)=14

The seven-bit penalty comes from using only 1% of the bare ADC range.

4. Try one real input

TryMove the control, predict the direction, then compare every output.

Target precision
Target gap
Conditioned levels
Conditioned exact bits
Conditioned minimum
Bare levels
Bare exact bits
Bare minimum
Range used

ObserveRelaxing the percentage target makes delta larger, reduces both required-level counts, and lowers the exact bit budgets.

ExplainThe ceiling makes hardware bits discrete, but the exact logarithm shows how close the design is to the next boundary.

Technical boundaries.

This is a transparent first-order teaching ledger tied to the chapter constants.

Noise
The calculation covers code spacing, not effective bits in noise.
Headroom
Conditioning must leave tolerance and fault headroom rather than fill the ADC exactly.
Accuracy
A resolvable code change is not automatically an accurate physical measurement.

Correct, not complete: this ledger does not select an ADC, gain stage, reference, or calibration plan.

5. Use the result in the design

Map the required physical change through sensor sensitivity, reserve headroom, then compare the calculated bits with effective-number-of-bits data.

6. Record the evidence state

Record physical span, sensitivity, gain, ADC span, headroom, target delta, calculated bits, ENOB, noise, and clipping tests.

7. Check yourself

Why round bits upward?
Answer: A fractional bit is unavailable in hardware, so the next whole bit is required.
Why does conditioning save bits?
Answer: Gain lets the signal occupy more of the ADC range instead of spending codes on unused voltage.
Do 14 nominal bits guarantee the target?
Answer: No. Noise and nonlinearity can reduce effective resolution below nominal bit depth.
Honesty boundary.

The arithmetic reproduces the named chapter case; it is an inspectable model, not a component approval.

Noise
The calculation covers code spacing, not effective bits in noise.
Headroom
Conditioning must leave tolerance and fault headroom rather than fill the ADC exactly.
Accuracy
A resolvable code change is not automatically an accurate physical measurement.

Correct, not complete: this ledger does not select an ADC, gain stage, reference, or calibration plan.

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