ADC Calculation Audit
ADC Calculation Audit
Ada checks resolution, range use, aliasing, and the noise floor behind the ADC example
ADA · CALCULATION AUDIT
ADC Calculation Audit
An ADC is a physics contract: the voltage step, sample clock, and anti-alias boundary decide whether firmware receives evidence or a polished false pattern.
The chapter’s worked example puts a temperature sensor that outputs 10 mV per 1 degree C onto a 12-bit ADC with a 3.3 V reference and 4096 possible codes, with the conditioned signal spanning 0.1 V to 1.75 V. The chapter claims this gives “enough amplitude detail for many temperature tasks” without yet proving the sample rate or calibration are sound. This audit asks the question that worked example invites: how many degrees does one ADC code actually represent, and how much of the converter’s 4096-code range does this sensor use?
Companion to the chapter Sampling and Aliasing — every number here comes from that chapter.
See the relationship before changing it
The figure reads from left to right. The blue card is adc resolution. The middle card applies this page's rule. The green card is ideal code width. Walk the arrows once: set the input, apply the rule, then read the result with its unit.
The retained audit below checks several chapter fixtures. This model keeps those stated values fixed and changes only adc resolution, so the numeric fixture does not switch without explanation.
Derive the baseline in four named moves
- 1
Name the input. The chapter baseline is 12 bits.
- 2
Name the relationship. code width = 3,300 mV / 2^bits
- 3
Substitute with units. 3,300 / 2^12 = 0.806 mV
- 4
Read the result. Keep the unit beside the value. Use it only inside the technical boundary on this page.
Predict, then change adc resolution
Try Predict the direction of code width = 3,300 mV / 2^bits. Test another adc resolution, then compare ideal code width.
Observe Each added bit halves the ideal voltage step before noise and calibration enter. Reset adc resolution to 12 and compare ideal code width.
Explain Each added bit halves the ideal voltage step before noise and calibration enter.
Check yourself
What should you do before trusting a moved-control result?
What does this small model leave out?
Start with Vref = 3.3 V and N = 12 bits, then check a 40 Hz signal at 100 samples/s and the 90 Hz interference fold.
The code step is 0.806 mV or 0.0806 °C on the stated sensor scale; 90 Hz sampled at 100 SPS appears as a false 10 Hz component.
Quantisation divides the reference into 4096 levels, while sampling maps frequencies separated by integer multiples of fs onto the same discrete-time frequency, creating aliases.
1. The 12-bit voltage step is small enough for the chapter's temperature scale
The worked example uses a 3.3 V reference and 4096 possible codes:
With the stated 10 mV per 1 degree C sensor scale, one code is 0.806 / 10 = 0.0806 degree C. The ideal half-LSB uncertainty is 0.806 / 2 = 0.403 mV, or 0.0403 degree C before real noise and calibration error are included.
2. Range use is reviewable, not a guess
The conditioned output spans from 0.1 V to 1.75 V:
That is exactly half of a 4096-code converter, which matches the chapter note that the design uses useful but not perfect code coverage.
3. Sampling math explains the alias warnings
For a useful signal up to 40 Hz, the mathematical lower boundary is more than 2 × 40 = 80 samples/s; real filters need margin above that. If unwanted frequencies reach the ADC, the fold calculation shows the false result:
| Check | Arithmetic shown | Audit result |
| 90 Hz interference at 100 SPS | round(90 / 100) = 1; |90 - 100·1| | 10 Hz alias |
| 1200 Hz component at 1000 SPS | round(1200 / 1000) = 1; |1200 - 1000·1| | 200 Hz alias |
| Ideal 12-bit SNR | 6.02 × 12 + 1.76 | 74.0 dB before real-world losses |
What the audit buys you: amplitude resolution, sample rate, and noise floor are separate gates. A 12-bit ADC can resolve the temperature example while still producing false evidence if the analog path lets high-frequency content fold into the sampled band.
Every number above is taken from this chapter's own worked example and re-derived step by step.
Technical boundaries: This ideal ADC audit omits reference tolerance and noise, input impedance, nonlinearity, clock jitter, anti-alias filter roll-off, sensor noise, clipping, and effective-number-of-bits loss.