The Jitter Budget as a Fraction of Cycle

The Jitter Budget as a Fraction of Cycle

Ada re-derives this chapter’s own numbers step by step, at full precision

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Ada ADA · CALCULATION AUDIT

The Jitter Budget as a Fraction of Cycle

The chapter’s jitter table quotes each application in mixed units — milliseconds in one row, microseconds in the next — hiding what really separates them. Put in one currency, three applications tolerate jitter of a full 10% of their cycle, while a printing press allows only 0.8% and semiconductor handling just 0.16% — 62.5x tighter. This audit converts the jitter budget to a fraction of cycle to reveal the harder constraint.

Companion to the chapter Real-Time and ISA-95 — every number here comes from that chapter.

See the relationship before changing it

The figure reads from left to right. The blue card is cycle time. The middle card applies the page rule. The green card is jitter fraction. Walk the arrows once: set the input, apply the rule, then read the result with its unit.

Cycle time changes jitter fraction An input card leads through the rule fraction = 0.1 us / cycle time x 100 to the jitter fraction result. INPUT PAGE INPUT APPLY THE RULE predict calculate check units OUTPUT RESULT
Walk the arrows. The fraction shows how tightly the clock must hold relative to one full cycle.

Derive the baseline in four named moves

  1. 1

    Name the input. The chapter baseline is 62.5 us.

  2. 2

    Name the relationship. fraction = 0.1 us / cycle time x 100

  3. 3

    Substitute with units. 0.1 / 62.5 x 100 = 0.16%

  4. 4

    Read the result. Keep the unit beside the value. Use it only inside the technical boundary on this page.

Predict, then change cycle time

Try Predict the direction of fraction = 0.1 us / cycle time x 100. Test another cycle time, then compare jitter fraction.

62.5 us
Chapter baseline
Jitter fraction

Observe The fraction shows how tightly the clock must hold relative to one full cycle. Reset cycle time to 62.5 and compare jitter fraction.

Explain The fraction shows how tightly the clock must hold relative to one full cycle.

Check yourself

What should you do before trusting a moved-control result?
Answer: Predict its direction, apply the shown relationship, keep the units, and reset to the worked baseline.
What does this small model leave out?
Answer: Only cycle time moves here. Field effects named in the technical boundary stay fixed.

Honesty note. This teaching model changes only cycle time. It is not a field prediction.

TryPress Check derivation after normalizing every cycle and jitter entry to microseconds, beginning with the 10% row.
ObserveThe normalized jitter-fraction column contracts from 10% through 0.8% to 0.16%, revealing a 62.5x constraint gap.
ExplainDividing maximum jitter by its own cycle time removes the mixed-unit disguise, so the smallest fraction identifies the strictest timing class.

Ada: The jitter table gives each application a cycle time and a maximum jitter, but they are quoted in mixed units — milliseconds in one row, microseconds in the next — so what really separates them is hidden. Let me put every row in one currency: jitter as a fraction of its own cycle time.

  • Simple I/O: 1 ms / 10 ms = 1000 us / 10,000 us = 0.10 — 10%, or 1 part in 10.
  • Process control: 10 ms / 100 ms = 0.10 — 10%, 1 part in 10.
  • Packaging machinery: 100 us / 1000 us = 0.10 — 10%, 1 part in 10.
  • Printing press: 1 us / 125 us = 0.008 — 0.8%, 1 part in 125.
  • Semiconductor handling: 0.1 us / 62.5 us = 0.0016 — 0.16%, 1 part in 625.

Three of the five applications share one budget: jitter may be a full tenth of the cycle. The printing press then demands 0.10 / 0.008 = 12.5x tighter timing, and semiconductor handling 0.10 / 0.0016 = 62.5x tighter still.

The design meaning is that the raw cycle time already told you semiconductor handling was fast — 62.5 us — but converting jitter to a fraction of cycle exposes the harder constraint: its timing has to hold to 1 part in 625, not 1 part in 10. That fractional budget, not the absolute speed, is why the chapter routes only these applications to hardware synchronization such as EtherCAT distributed clocks or IEEE 1588, where a bounded clock matters more than a merely fast link.

Technical boundaries
The fraction comparison has no scheduler interference, oscillator noise, hop variation, synchronization error, or tail distribution; each row is one stated limit divided by one cycle.

Work the audit first, then check the displayed derivation.

Every number above is taken from the chapter’s own material and re-derived step by step.