Ada Audits the PWM-to-DAC Selection Numbers
Ada re-derives this chapter’s own numbers step by step, at full precision
ADA · CALCULATION AUDIT
Ada Audits the PWM-to-DAC Selection Numbers
An 8-bit PWM at code 200 on a 3.3 V rail averages to 2.59 V, but a fixed 10.24 MHz timer that gives 40 kHz at 8 bits drops to 2.5 kHz at 12 bits, and a 20 kHz PWM through a 0.22 uF RC filter trades ripple for an 11 ms settling delay. Reaching for a DAC instead swaps the switching carrier for quantization steps. This audit re-derives each figure and asks which limit — average voltage, timer frequency, RC settling, or DAC quantization — is actually the active one behind a PWM-versus-DAC choice.
Companion to the chapter Applied: PWM vs DAC Output — every number here comes from that chapter.
Ada: A PWM output choice is only defensible when the arithmetic says which limit is active: average voltage, timer frequency, RC settling, or DAC quantization.
1. Duty-cycle averaging comes before load physics. The chapter's 30% and code-200 examples both start by converting a duty fraction into an average voltage.
2. Timer resolution spends frequency. With the stated 10.24 MHz timer clock, 12-bit PWM gives 16 times more duty positions than 8-bit PWM, but the PWM carrier falls by the same factor.
3. RC smoothing trades ripple for delay. The chapter's 20 kHz, 10 kohm, 0.22 uF filter pushes the carrier far above cutoff, but the same RC product sets the response time.
4. A DAC removes the carrier but keeps quantization. On the same 3.3 V rail, a 12-bit DAC has small voltage steps and no 20 kHz switching component to filter.
Selection rule: use PWM when the load naturally averages energy and the timer still meets the frequency target. Use a DAC when switching ripple or settling delay is the dominant error.
Every number above is taken from the chapter’s own material and re-derived step by step.