PWM-to-DAC Selection Calculation Audit

PWM-to-DAC Selection Calculation Audit

Ada re-derives this chapter’s own numbers step by step, at full precision

foundations
math-foundations
calculation-audit
electronics
beginner
Ada ADA · CALCULATION AUDIT

PWM-to-DAC Selection Calculation Audit

An 8-bit PWM at code 200 on a 3.3 V rail averages to 2.59 V, but a fixed 10.24 MHz timer that gives 40 kHz at 8 bits drops to 2.5 kHz at 12 bits, and a 20 kHz PWM through a 0.22 uF RC filter trades ripple for an 11 ms settling delay. Reaching for a DAC instead swaps the switching carrier for quantization steps. This audit re-derives each figure and asks which limit — average voltage, timer frequency, RC settling, or DAC quantization — is actually the active one behind a PWM-versus-DAC choice.

Companion to the chapter Applied: PWM vs DAC Output — every number here comes from that chapter.

Ada: A PWM output choice is only defensible when the arithmetic says which limit is active: average voltage, timer frequency, RC settling, or DAC quantization.

See the relationship before changing it

The figure reads from left to right. The blue card is eight-bit pwm code. The middle card applies this page's rule. The green card is ideal average voltage. Walk the arrows once: set the input, apply the rule, then read the result with its unit.

The retained audit below checks several chapter fixtures. This model keeps those stated values fixed and changes only eight-bit pwm code, so the numeric fixture does not switch without explanation.

Eight-bit PWM code changes ideal average voltage An input card leads through the rule average = 3.3 V x code / 255 to the ideal average voltage result. INPUT PAGE INPUT APPLY THE RULE predict calculate check units OUTPUT RESULT
Walk the arrows. A larger PWM code raises ideal average voltage while timer frequency and filter settling remain separate limits.

Derive the baseline in four named moves

  1. 1

    Name the input. The chapter baseline is 200 code.

  2. 2

    Name the relationship. average = 3.3 V x code / 255

  3. 3

    Substitute with units. 3.3 x 200 / 255 = 2.588 V

  4. 4

    Read the result. Keep the unit beside the value. Use it only inside the technical boundary on this page.

Predict, then change eight-bit pwm code

Try Predict the direction of average = 3.3 V x code / 255. Test another eight-bit pwm code, then compare ideal average voltage.

200 code
Chapter baseline
Ideal average voltage

Observe A larger PWM code raises ideal average voltage while timer frequency and filter settling remain separate limits. Reset eight-bit pwm code to 200 and compare ideal average voltage.

Explain A larger PWM code raises ideal average voltage while timer frequency and filter settling remain separate limits.

Check yourself

What should you do before trusting a moved-control result?
Answer: Predict its direction, apply the shown relationship, keep the units, and reset to the worked baseline.
What does this small model leave out?
Answer: Only eight-bit pwm code moves here. Field effects named in the technical boundary stay fixed.

Honesty note. This teaching model changes only eight-bit pwm code. It is not a field prediction.

Try

Choose Calculate for PWM code 200 at 3.3 V, a 10.24 MHz timer, and the 20 kHz RC-filter case.

Observe

The audit returns 2.59 V average, 40 kHz at 8 bits versus 2.5 kHz at 12 bits, and 11 ms filter settling.

Explain

Extra timer resolution consumes counter frequency, while stronger RC smoothing consumes response time; a DAC avoids switching ripple when those costs exceed the load's tolerance.

Technical boundaries

For the PWM selection, excluded from this fixed arithmetic are load impedance changes, switching losses, timer jitter, DAC settling transients, or filter-component tolerances.

1. Duty-cycle averaging comes before load physics. The chapter's 30% and code-200 examples both start by converting a duty fraction into an average voltage.

30% LED case: D = 0.30; Vavg = 0.30 * 3.3 V = 0.990 V
8-bit code 200: D = 200 / 255 = 0.7843137; Vavg = 0.7843137 * 3.3 V = 2.588235 V, rounded at the end to 2.59 V

2. Timer resolution spends frequency. With the stated 10.24 MHz timer clock, 12-bit PWM gives 16 times more duty positions than 8-bit PWM, but the PWM carrier falls by the same factor.

8-bit PWM: 10.24 MHz / 2^8 = 10,240,000 / 256 = 40,000 Hz = 40 kHz
12-bit PWM: 10.24 MHz / 2^12 = 10,240,000 / 4096 = 2,500 Hz = 2.5 kHz; frequency ratio = 40,000 / 2,500 = 16

3. RC smoothing trades ripple for delay. The chapter's 20 kHz, 10 kohm, 0.22 uF filter pushes the carrier far above cutoff, but the same RC product sets the response time.

RC = 10,000 ohm * 0.22 uF = 10,000 * 0.00000022 F = 0.0022 s = 2.2 ms
fc = 1 / (2 * pi * 0.0022) = 72.343 Hz; carrier ratio = 20,000 / 72.343 = 276.46x
settling estimate = 5 * RC = 5 * 2.2 ms = 11.0 ms

4. A DAC removes the carrier but keeps quantization. On the same 3.3 V rail, a 12-bit DAC has small voltage steps and no 20 kHz switching component to filter.

12-bit DAC code 2048: 3.3 V * 2048 / 4095 = 1.650403 V, rounded at the end to 1.650 V
one-code step = 3.3 V / 4095 = 0.000805861 V = 0.805861 mV

Selection rule: use PWM when the load naturally averages energy and the timer still meets the frequency target. Use a DAC when switching ripple or settling delay is the dominant error.

Every number above is taken from the chapter’s own material and re-derived step by step.