Core Networking · Study deck

SPI Protocol

A controller reads an accelerometer correctly until a display is added to the same serial bus.

Packet Pete is your guide for this deck.

wiredcomm

Packet Pete, the module guide, in a scene from this chapter.

After studying this chapter

Learning objectives

You will be able to:

Explain: That visual pairing grounds mosi carries controller-to-peripheral bits, miso carries peripheral-to-controller bits, sclk times the transfer, and cs frames the selected device in named evidence.
Explain: Its diagram makes SPI Bus Architecture with Multiple Slaves and: CS1 explicit within adding peripherals usually adds chip-select wiring and firmware bookkeeping, not bus addresses.
Explain: The visual evidence for under the hood: the bus is fast because it is simple sits in Figure: SPI is one member of the serial toolkit.
Explain: The next sensor read needs to restore its timing contract before asserting select.

Major section

Start With Speed and Selection

The wires are connected, yet the two parts disagree about when a bit is valid and which byte begins the record.

Serial Peripheral Interface (SPI) is a short wired link in which a controller supplies a clock and selects one connected part at a time.
A protocol is the agreed order and meaning of that exchange.
One clean bench trace does not cover cable length, noise, or every vendor detail.

Major section

Overview: SPI Trades Wires For Deterministic Transfers

That visual pairing grounds mosi carries controller-to-peripheral bits, miso carries peripheral-to-controller bits, sclk times the transfer, and cs frames the selected device in named evidence.

That sequence keeps overview: spi trades wires for deterministic transfers tied to what is visibly labelled.

MOSI carries controller-to-peripheral bits, MISO carries peripheral-to-controller bits, SCLK times the transfer, and CS frames the selected device.

Major section

Overview: SPI Trades Wires For Deterministic Transfers (continued)

The next claim about overview: spi trades wires for deterministic transfers depends on Figure: Adding peripherals usually adds chip-select wiring and firmware.

Its diagram makes SPI Bus Architecture with Multiple Slaves and: CS1 explicit within adding peripherals usually adds chip-select wiring and firmware bookkeeping, not bus addresses.
Locate SPI Bus Architecture with Multiple Slaves on Figure: Adding peripherals usually adds chip-select wiring and firmware before checking: CS1.
The visual's third anchor,: CS2, completes adding peripherals usually adds chip-select wiring and firmware bookkeeping, not bus addresses.

Major section

Under The Hood: The Bus Is Fast Because It Is Simple

Together those labels make the digital protocol assumes a clean electrical interface: compatible levels, a controlled return path, and only one selected miso driver testable.

The visual evidence for under the hood: the bus is fast because it is simple sits in Figure: SPI is one member of the serial toolkit.

The digital protocol assumes a clean electrical interface: compatible levels, a controlled return path, and only one selected MISO driver.

Major section

Clock a Register Read after Selecting the Right Peripheral

The controller must provide 3 × 8 = 24 clock cycles.

At 2 MHz, the ideal shift time is 24 divided by 2,000,000 = 12 microseconds.
Full-duplex shifting means bits travel both ways during each clock cycle.
The received byte during the command phase may be dummy data under this sensor's contract.

Major section

Clock a Register Read after Selecting the Right Peripheral (continued)

A driver that treats all three received bytes as measurements can create an offset error while the electrical trace remains perfectly regular.

A matching clock frequency is insufficient if the controller samples while the peripheral is changing the signal.
The next sensor read needs to restore its timing contract before asserting select.
Two peripherals driving MISO can corrupt data or cause electrical contention; normal firmware must prevent that state.

Major section

Clock a Register Read after Selecting the Right Peripheral (continued)

An unchanged register is a better first timing check than a moving acceleration signal, because its expected bytes are known.

The module's interface lesson is that a simple serial mechanism moves responsibility into the driver and board design.
Explicit framing, mode ownership and readback checks let multiple peripherals share wires without pretending they share one universal command language.
Component documentation and measured setup and hold margins determine the final rate.

Deck summary

Key takeaways

The wires are connected, yet the two parts disagree about when a bit is valid and which byte begins the record.

That visual pairing grounds mosi carries controller-to-peripheral bits, miso carries peripheral-to-controller bits, sclk times the transfer, and cs frames the selected device in named evidence.
The next claim about overview: spi trades wires for deterministic transfers depends on Figure: Adding peripherals usually adds chip-select wiring and firmware.
Together those labels make the digital protocol assumes a clean electrical interface: compatible levels, a controlled return path, and only one selected miso driver testable.
The controller must provide 3 × 8 = 24 clock cycles.

Retrieval practice

Recall check 1 of 3

Packet Pete says: answer from memory, then check your reasoning.

Q1What is the core SPI tradeoff compared with a shared-address bus such as I2C?

ASPI shares one bidirectional address line, so adding devices rarely changes wiring.

BSPI offers simple high-throughput framed transfers, but usually needs a chip-select line per device.

CSPI discovers peripherals by scanning bus addresses, so firmware does not map chip selects.

DSPI is optimized for long building cable runs rather than short board-level peripherals.

Show answer

Answer: B SPI keeps the transaction simple and clocked by the controller, but the design pays in chip-select wiring and routing.

Retrieval practice

Recall check 2 of 3

Packet Pete says: answer from memory, then check your reasoning.

Q2A sensor returns a recognizable register value, but every read appears shifted by one bit. Which SPI contract field should be checked first?

AChip-select inventory, because the selected device count changes each byte boundary.

BPull-up resistor value, because SPI addressing depends on the bus idle voltage.

CClock polarity and phase; the wrong sampling edge can shift the received bit stream.

DController IP address, because network addressing determines register alignment.

Show answer

Answer: C A CPOL or CPHA mismatch often produces shifted or corrupted bytes even when the four wires are connected.

Retrieval practice

Recall check 3 of 3

Packet Pete says: answer from memory, then check your reasoning.

Q3Why can an SPI link pass a simple bench test but fail on the final product board?

AAccept matching SCLK and mode settings as proof that the final board matches the bench.

BAdd firmware retries to absorb occasional read errors while keeping the bench wiring assumptions.

CCheck chip-select software timing and assume deselected peripherals release MISO as specified.

DValidate final-board trace length, loading, grounding, chip-select routing, and MISO release behavior.

Show answer

Answer: D SPI is sensitive to timing and board-level electrical assumptions, so the production layout must be validated, not inferred from a short bench wire.

Print reference

Answers

Answer key.

B · SPI keeps the transaction simple and clocked by the controller, but the design pays in chip-select wiring and routing.
C · A CPOL or CPHA mismatch often produces shifted or corrupted bytes even when the four wires are connected.
D · SPI is sensitive to timing and board-level electrical assumptions, so the production layout must be validated, not inferred from a short bench wire.