Core Networking · Study deck

SPI Protocol

A controller reads an accelerometer correctly until a display is added to the same serial bus.

Packet Pete is your guide for this deck.

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After studying this chapter

Learning objectives

You will be able to:

Explain: Four wires do all the work here, and each name already encodes a direction. Figure: SPI wiring diagram shows an ESP32 master connected maps them between a controller and an SD card.
Explain: A single platform block sits at the centre with dashed lines to the panels around it, and the one substantive label says that each serial protocol is strongest in a different use.
Explain: The two boxes in Figure: SPI wiring diagram shows an ESP32 master connected are a controller and a card, with four wires between them and a legend that expands every name.

Major section

Start With Speed and Selection

The wires are connected, yet the two parts disagree about when a bit is valid and which byte begins the record.

Serial Peripheral Interface (SPI) is a short wired link in which a controller supplies a clock and selects one connected part at a time.
A protocol is the agreed order and meaning of that exchange.
One clean bench trace does not cover cable length, noise, or every vendor detail.

Protocol selection should start from distance, device count, data rate, reliability, and available pins rather than from habit.

Major section

Overview: SPI Trades Wires For Deterministic Transfers

MOSI carries controller-to-peripheral data while MISO carries peripheral-to-controller data, so a bit can move in each direction during the same clock cycle.

Deasserting SS ends the frame and should release that peripheral's MISO driver.
Three wires in Figure: Adding peripherals usually adds chip-select wiring and firmware run to every peripheral at once: the clock and the two data lines.
Those do not multiply.

MOSI carries controller-to-peripheral bits, MISO carries peripheral-to-controller bits, SCLK times the transfer, and CS frames the selected device.

Major section

Practitioner: Treat Each Peripheral As A Timing Contract

Their two binary choices produce four modes; a controller in mode 0 and a peripheral expecting mode 3 can appear active while sampling unstable bits.

The mode is therefore a shared endpoint contract, not a controller preference.
Four wires do all the work here, and each name already encodes a direction. Figure: SPI wiring diagram shows an ESP32 master connected maps them between a controller and an SD card.
The two boxes in Figure: SPI wiring diagram shows an ESP32 master connected are a controller and a card, with four wires between them and a legend that expands every name.

CPOL and CPHA decide the idle clock level and which edge samples data. A mode mismatch can corrupt every byte while the wiring looks correct.

Major section

Practitioner: Treat Each Peripheral As A Timing Contract (continued)

Two carry data in opposite directions at the same time, which is what full duplex means here: a byte goes out while a byte comes back.

The third is the clock, and the note that the controller generates it is the reason the card never sets the speed.
The fourth is chip select, marked active low, so the card listens only while that line is held down.
The strip underneath states the trade plainly: no addresses, a separate select line per device, and a clock measured in megahertz.

Adding peripherals usually adds chip-select wiring and firmware bookkeeping, not bus addresses.

Major section

Under The Hood: The Bus Is Fast Because It Is Simple

Their logic levels must be compatible, their return path controlled, and their edges clean enough at the receiver.

Unselected peripherals must release MISO so two outputs do not contend.
Longer traces, connectors, level shifters, or many loads can add delay and ringing that a slower bench setup hides.
The SPI interface is accepted only when timing and voltage are measured at the receiving pins under the intended rate and topology.

The digital protocol assumes a clean electrical interface: compatible levels, a controlled return path, and only one selected MISO driver.

Major section

Under The Hood: The Bus Is Fast Because It Is Simple (continued)

Figure: SPI is one member of the serial toolkit is a schematic rather than a comparison table.

A single platform block sits at the centre with dashed lines to the panels around it, and the one substantive label says that each serial protocol is strongest in a different use.
Nothing in the drawing ranks the buses or gives a speed, a distance or a pin count, and it should not be quoted as though it did.
For a short link, ask how many devices share it and whether they need full duplex or high sustained rate.

Major section

Clock a Register Read after Selecting the Right Peripheral

The controller must provide 3 × 8 = 24 clock cycles.

At 2 MHz, the ideal shift time is 24 divided by 2,000,000 = 12 microseconds.
Full-duplex shifting means bits travel both ways during each clock cycle.
The received byte during the command phase may be dummy data under this sensor's contract.

Major section

Clock a Register Read after Selecting the Right Peripheral (continued)

A driver that treats all three received bytes as measurements can create an offset error while the electrical trace remains perfectly regular.

A matching clock frequency is insufficient if the controller samples while the peripheral is changing the signal.
The next sensor read needs to restore its timing contract before asserting select.
Two peripherals driving MISO can corrupt data or cause electrical contention; normal firmware must prevent that state.

SPI wiring diagram shows an ESP32 master connected to an SD-card slave by MOSI, MISO, clock and an active-low chip-select line. It labels full-duplex operation and separate chip-select pins for additional slaves.

Major section

Clock a Register Read after Selecting the Right Peripheral (continued)

An unchanged register is a better first timing check than a moving acceleration signal, because its expected bytes are known.

The module's interface lesson is that a simple serial mechanism moves responsibility into the driver and board design.
Explicit framing, mode ownership and readback checks let multiple peripherals share wires without pretending they share one universal command language.
Component documentation and measured setup and hold margins determine the final rate.

SPI is one member of the serial toolkit. It is a good board-level peripheral bus, not a replacement for every wired interface.

Deck summary

Key takeaways

The wires are connected, yet the two parts disagree about when a bit is valid and which byte begins the record.

MOSI carries controller-to-peripheral data while MISO carries peripheral-to-controller data, so a bit can move in each direction during the same clock cycle.
Their two binary choices produce four modes; a controller in mode 0 and a peripheral expecting mode 3 can appear active while sampling unstable bits.
Two carry data in opposite directions at the same time, which is what full duplex means here: a byte goes out while a byte comes back.
The controller must provide 3 × 8 = 24 clock cycles.

Retrieval practice

Recall check 1 of 4

Packet Pete says: answer from memory, then check your reasoning.

Q1What is the core SPI tradeoff compared with a shared-address bus such as I2C?

ASPI shares one bidirectional address line, so adding devices rarely changes wiring.

BSPI discovers peripherals by scanning bus addresses, so firmware does not map chip selects.

CSPI is optimized for long building cable runs rather than short board-level peripherals.

DSPI offers simple high-throughput framed transfers, but usually needs a chip-select line per device.

Show answer

Answer: D SPI keeps the transaction simple and clocked by the controller, but the design pays in chip-select wiring and routing.

Retrieval practice

Recall check 2 of 4

Packet Pete says: answer from memory, then check your reasoning.

Q2Two SPI peripherals share a return-data line. Reads fail only when both are fitted. What must the bus contract verify?

AVerify payload labels because the exchanged values show that the shared return line is driven correctly.

BVerify chip-select timing and idle-device release of the shared return line.

CVerify cloud broker acceptance alone rather than shared-wire behavior.

DVerify both chip selects stay active during each read on the shared line.

Show answer

Answer: B A deselected part that still drives the shared line can corrupt the selected part's reply.

Retrieval practice

Recall check 3 of 4

Packet Pete says: answer from memory, then check your reasoning.

Q3A sensor returns a recognizable register value, but every read appears shifted by one bit. Which SPI contract field should be checked first?

AChip-select timing and device selection across the register read.

BInput pull-up strength on the SPI data line during the register read.

CClock polarity and phase; the wrong sampling edge can shift the received bit stream.

DThe controller's network interface configuration for the sensor register map and its endpoint address.

Show answer

Answer: C A CPOL or CPHA mismatch often produces shifted or corrupted bytes even when the four wires are connected.

Retrieval practice

Recall check 4 of 4

Packet Pete says: answer from memory, then check your reasoning.

Q4Why can an SPI link pass a simple bench test but fail on the final product board?

AAccept matching SCLK and mode settings as proof that the final board matches the bench.

BValidate final-board trace length, loading, grounding, chip-select routing, and MISO release behavior.

CAdd firmware retries to absorb occasional read errors while keeping the bench wiring assumptions.

DCheck chip-select software timing and assume deselected peripherals release MISO as specified.

Show answer

Answer: B SPI is sensitive to timing and board-level electrical assumptions, so the production layout must be validated, not inferred from a short bench wire.

Print reference

Answers

Answer key.

D · SPI keeps the transaction simple and clocked by the controller, but the design pays in chip-select wiring and routing.
B · A deselected part that still drives the shared line can corrupt the selected part's reply.
C · A CPOL or CPHA mismatch often produces shifted or corrupted bytes even when the four wires are connected.
B · SPI is sensitive to timing and board-level electrical assumptions, so the production layout must be validated, not inferred from a short bench wire.