Core Networking · Study deck

I2C: Bring-Up and Diagnosis

The bus rules are known, but a real sensor still may not answer.

Packet Pete is your guide for this deck.

wiredcomm

Packet Pete, the module guide, in a scene from this chapter.

After studying this chapter

Learning objectives

You will be able to:

Explain: That makes the bus simple, but it also means one wrong device, weak pull-up, duplicate address, voltage mismatch, or stuck line can affect every device on the bus.
Explain: With a smaller pull-up, the edge is faster, but every device must be able to pull the line below the valid-low threshold while sinking the extra current.
Explain: A design that moves from 4.7 kohm to 2.2 kohm may fix a 400 kHz rise-time failure, but it also changes power and VOL margin.
Explain: Two shared wires:: SDA carries address and data.

Major section

Calculate Pull-Up Resistors

Choosing the right pull-up resistor value is the single most common source of I2C failures.

Too high and the bus cannot rise fast enough; too low and the devices cannot sink enough current to pull the bus low.
Minimum resistor (max current):: I2C spec limits sink current to 3 mA at V~OL~ = 0.4 V.
Maximum resistor (rise time):: The bus must rise from 0V to 70% of VCC within the rise time specification.

Major section

Calculate Pull-Up Resistors (continued)

Rise time depends on bus capacitance.

Where the maximum rise time is 1000 ns for standard mode (100 kHz) and 300 ns for fast mode (400 kHz).
Result:: For this 3-device bus at 400 kHz, use pull-ups between 967 Ω and 6.68 kohm.
The standard 4.7 kohm falls comfortably in the middle -- which is why 4.7 kohm is the universal default recommendation.

Major section

I2C Shared-Bus Reliability Record

That makes the bus simple, but it also means one wrong device, weak pull-up, duplicate address, voltage mismatch, or stuck line can affect every device on the bus.

The firmware call that says read register 0xF7 from address 0x76 only succeeds when the physical bus, address phase, ACK bits, timing, and recovery assumptions all hold together.

I2C reliability is built from linked layers: shared open-drain wiring, an address byte with a read/write bit, ACK slots after each byte, and transaction framing with START, repeated START, and STOP conditions.

Major section

I2C Shared-Bus Reliability Record (continued)

Good I2C design is therefore not just picking a library.

The overview decision is whether the bus boundary is appropriate for the job.
I2C is a strong fit for short, local, board-level communication where the controller owns the transaction schedule and peripherals are close enough that capacitance stays controlled.
SCL provides timing.

Major section

I2C Shared-Bus Reliability Record (continued)

That sequence keeps i2c shared-bus reliability record tied to what is visibly labelled.

Two shared wires:: SDA carries address and data.
Every attached device sees both lines, so wiring length, module count, connector quality, and breadboard capacitance accumulate into one bus limit.
Duplicate fixed addresses make two devices answer at once; reserved addresses and shifted address bytes create equally confusing scanner results.

Major section

Rise Time Sets the Real I2C Speed

I2C looks digital in code, but the rising edge is analog.

The receiver samples logic levels at clocked moments; if the edge is still rising, the bus can fail only at higher speed or only with every device attached.
The useful mental model is an RC charge curve.
The debug path is to separate causes.

Major section

Rise Time Sets the Real I2C Speed (continued)

A design that moves from 4.7 kohm to 2.2 kohm may fix a 400 kHz rise-time failure, but it also changes power and VOL margin.

With a larger pull-up resistor, the device sinks less current when it pulls low, but the high transition is slower.
If a device appears at 100 kHz but fails at 400 kHz, inspect rise time and capacitance.
The same physical rule explains multi-master arbitration.

Major section

Rise Time Sets the Real I2C Speed (continued)

With a smaller pull-up, the edge is faster, but every device must be able to pull the line below the valid-low threshold while sinking the extra current.

Each controller watches SDA while transmitting; if it releases the line high but another controller pulls it low, it has lost arbitration and must stop driving.
The software still needs ownership rules, bounded retries, and logging that distinguishes arbitration loss from a missing slave ACK.
Rise-time limit:: The pull-up resistor and bus capacitance define whether the line reaches a valid high level before the next clock sample.

Major section

Rise Time Sets the Real I2C Speed (continued)

Fast mode leaves far less time for the same edge than standard mode.

Firmware must tolerate this within a bounded timeout, and the timeout should be measured against the slowest real device on the bus.
Bus lockup:: A reset or interrupted transaction can leave SDA low.
The master needs an explicit recovery sequence, commonly clocking SCL until the slave releases SDA, then issuing STOP and reinitializing the peripheral.

Deck summary

Key takeaways

Choosing the right pull-up resistor value is the single most common source of I2C failures.

Rise time depends on bus capacitance.
That makes the bus simple, but it also means one wrong device, weak pull-up, duplicate address, voltage mismatch, or stuck line can affect every device on the bus.
Good I2C design is therefore not just picking a library.
That sequence keeps i2c shared-bus reliability record tied to what is visibly labelled.

Retrieval practice

Recall check 1 of 3

Packet Pete says: answer from memory, then check your reasoning.

Q1An Arduino connects to a BME280 sensor (I2C address 0x76) and an OLED display (I2C address 0x3C) on the same I2C bus. Both devices ACK their addresses. What happens if you send data to 0x76 without specifying it's a write vs read operation?

ABoth devices receive the data because I2C is broadcast

BOLED receives the data because lower addresses have priority

CBus collision occurs; both devices are damaged

DThe BME280 responds; the address byte's R/W bit sets direction

Show answer

Answer: D I2C addresses are 7-bit, transmitted in the most significant 7 bits of the first byte.

Retrieval practice

Recall check 2 of 3

Packet Pete says: answer from memory, then check your reasoning.

Q2Place each I2C event where it lives in the transaction so you can diagnose whether a bus failure happens before, during, or after device selection.

APull-Up Idle Bus

BSTART Condition

CAddress Frame

DACK Slot

EData and STOP

Show answer

Answer: A The map separates electrical bus control, device selection, and payload closure so you can locate a failed I2C transaction before reaching for a logic analyser.

Q3Complete the I2C address-byte rule for a 7-bit device address.

Aif read:

Bif addr == 0:

Cif read == None:

Dif addr > 0x77:

Show answer

Answer: A I2C sends the 7-bit address in bits 7 through 1 of the first byte.

Retrieval practice

Recall check 3 of 3

Packet Pete says: answer from memory, then check your reasoning.

Q4A sensor responds correctly at 100 kHz, but disappears from the I2C scanner at 400 kHz after two more modules and 30 cm of jumper wire are added. What should be checked first?

ABus capacitance, pull-ups, and rise time.

BThe cloud endpoint for the sensor data

COnly the 7-bit address, because speed never affects I2C discovery

DWhether SPI chip-select is asserted

Show answer

Answer: A Adding devices and wire increases capacitance.

Print reference

Answers

Answer key.

D · I2C addresses are 7-bit, transmitted in the most significant 7 bits of the first byte.
A · The map separates electrical bus control, device selection, and payload closure so you can locate a failed I2C transaction before reaching for a logic analyser.
A · I2C sends the 7-bit address in bits 7 through 1 of the first byte.
A · Adding devices and wire increases capacitance.