Core Networking · Study deck

I2C: Bring-Up and Diagnosis

The bus rules are known, but a real sensor still may not answer.

Packet Pete is your guide for this deck.

wiredcomm

Packet Pete, the module guide, in a scene from this chapter.

After studying this chapter

Learning objectives

You will be able to:

bring up a BME280 on an I2C bus
diagnose pull-up and clock-stretching failures
verify arbitration and transaction evidence
Explain: Scenario: You're designing a robotics platform with two microcontrollers (ESP32 and Arduino) that both need to control a shared OLED display (I2C address 0x3C) and BME280 sensor (0x76).

Major section

Check I²C Arbitration

Scenario: You're designing a robotics platform with two microcontrollers (ESP32 and Arduino) that both need to control a shared OLED display (I2C address 0x3C) and BME280 sensor (0x76).

This mechanism avoids the direct high-versus-low driver contention that push-pull outputs could cause if wired together incorrectly.
The trade-off is that RC charging through pull-up resistors limits rise time.
SPI's push-pull lines commonly run at tens of MHz.

Major section

Check I²C Arbitration (continued)

Standard-mode I2C reaches 100 kHz and Fast-mode reaches 400 kHz; supported devices and bus conditions can also permit Fast-mode Plus at 1 MHz or High-speed mode at 3.4 MHz.

This exceeds Standard-mode's 1.0 µs limit and Fast-mode's 0.30 µs limit.
Smaller pull-ups give faster rise times, but no fixed resistor works for every bus.
Even 2.2 kΩ gives 0.746 µs at 400 pF, still too slow for Fast-mode; reduce capacitance or choose a pull-up within the device's sink-current limit.

Major section

Calculate Pull-Up Resistors

Rise time depends on bus capacitance.

Choosing the right pull-up resistor value is the single most common source of I2C failures.
Too high and the bus cannot rise fast enough; too low and the devices cannot sink enough current to pull the bus low.
A scope shows rounded edges (too slow) or ringing.

Major section

Calculate Pull-Up Resistors (continued)

Minimum resistor (max current):: For this Standard/Fast-mode example, use a device rated to sink 3 mA while keeping V~OL~ at or below 0.4 V.

Maximum resistor (rise time):: The specified rise-time interval is from 30% to 70% of VCC.
Where the maximum rise time is 1000 ns for standard mode (100 kHz) and 300 ns for fast mode (400 kHz).
Result: For this 3.3 V, 53 pF bus at 400 kHz, the calculated pull-up window is 967 Ω to 6.68 kohm.

Major section

I2C Shared-Bus Reliability Record

That makes the bus simple, but it also means one wrong device, weak pull-up, duplicate address, voltage mismatch, or stuck line can affect every device on the bus.

The firmware call that says read register 0xF7 from address 0x76 only succeeds when the physical bus, address phase, ACK bits, timing, and recovery assumptions all hold together.

I2C reliability is built from linked layers: shared open-drain wiring, an address byte with a read/write bit, ACK slots after each byte, and transaction framing with START, repeated START, and STOP conditions.

Major section

I2C Shared-Bus Reliability Record (continued)

Good I2C design is therefore not just picking a library.

The overview decision is whether the bus boundary is appropriate for the job.
I2C is a strong fit for short, local, board-level communication where the controller owns the transaction schedule and peripherals are close enough that capacitance stays controlled.
SCL provides timing.

Major section

I2C Shared-Bus Reliability Record (continued)

The device answers, and that answer is the whole point: an addressed part confirms every byte it accepts, so a missing confirmation is the first hard evidence of a wiring, address or voltage fault.

The controller then declines the next byte and closes the bus, which is how the device learns the transaction ended.
Two shared wires: SDA carries address and data.
Every attached device sees both lines, so wiring length, module count, connector quality, and breadboard capacitance accumulate into one bus limit.
Duplicate fixed addresses make two devices answer at once; reserved addresses and shifted address bytes create equally confusing scanner results.

Major section

Rise Time Sets the Real I2C Speed

I2C looks digital in code, but the rising edge is analog.

The receiver samples logic levels at clocked moments; if the edge is still rising, the bus can fail only at higher speed or only with every device attached.
The useful mental model is an RC charge curve.
The debug path is to separate causes.

Major section

Rise Time Sets the Real I2C Speed (continued)

A design that moves from 4.7 kohm to 2.2 kohm may fix a 400 kHz rise-time failure, but it also changes power and VOL margin.

With a larger pull-up resistor, the device sinks less current when it pulls low, but the high transition is slower.
If a device appears at 100 kHz but fails at 400 kHz, inspect rise time and capacitance.
The same physical rule explains multi-master arbitration.

I2C provides a simple, efficient interface for connecting low-speed peripherals like sensors, EEPROMs, and displays. Its two-wire design minimizes PCB routing complexity while supporting multiple devices.

Major section

Rise Time Sets the Real I2C Speed (continued)

With a smaller pull-up, the edge is faster, but every device must be able to pull the line below the valid-low threshold while sinking the extra current.

Each controller watches SDA while transmitting; if it releases the line high but another controller pulls it low, it has lost arbitration and must stop driving.
The software still needs ownership rules, bounded retries, and logging that distinguishes arbitration loss from a missing slave ACK.
Rise-time limit: The pull-up resistor and bus capacitance define whether the line reaches a valid high level before the next clock sample.

Major section

Rise Time Sets the Real I2C Speed (continued)

Fast mode leaves far less time for the same edge than standard mode.

Firmware must tolerate this within a bounded timeout, and the timeout should be measured against the slowest real device on the bus.
Bus lockup: A reset or interrupted transaction can leave SDA low.
The master needs an explicit recovery sequence, commonly clocking SCL until the slave releases SDA, then issuing STOP and reinitializing the peripheral.

Deck summary

Key takeaways

Scenario: You're designing a robotics platform with two microcontrollers (ESP32 and Arduino) that both need to control a shared OLED display (I2C address 0x3C) and BME280 sensor (0x76).

Standard-mode I2C reaches 100 kHz and Fast-mode reaches 400 kHz; supported devices and bus conditions can also permit Fast-mode Plus at 1 MHz or High-speed mode at 3.4 MHz.
Rise time depends on bus capacitance.
Minimum resistor (max current):: For this Standard/Fast-mode example, use a device rated to sink 3 mA while keeping V~OL~ at or below 0.4 V.
Good I2C design is therefore not just picking a library.

Retrieval practice

Recall check 1 of 3

Packet Pete says: answer from memory, then check your reasoning.

Q1An Arduino connects to a BME280 sensor (I2C address 0x76) and an OLED display (I2C address 0x3C) on the same I2C bus. Both devices ACK their addresses. What happens when the controller sends data to 0x76 with the address byte's R/W bit set to write?

AThe BME280 responds; the address byte's R/W bit sets direction

BBoth devices receive the data because I2C is broadcast

COLED receives the data because lower addresses have priority

DBus collision occurs; both devices are damaged

Show answer

Answer: A For a normal 7-bit addressed transfer, bits [7:1] carry 0x76 and bit 0 selects write (0) or read (1).

Retrieval practice

Recall check 2 of 3

Packet Pete says: answer from memory, then check your reasoning.

Q2What I2C interval confirms that the receiver accepted the preceding byte by pulling SDA low?

AACK Slot

BPull-Up Idle Bus

CSTART Condition

DAddress Frame

Show answer

Answer: A The receiver pulls SDA low to confirm that the preceding byte was accepted.

Q3Complete the I2C address-byte rule for a 7-bit device address.

Aif read:

Bif addr == 0:

Cif read == None:

Dif addr > 0x77:

Show answer

Answer: A I2C sends the 7-bit address in bits 7 through 1 of the first byte.

Retrieval practice

Recall check 3 of 3

Packet Pete says: answer from memory, then check your reasoning.

Q4A sensor responds correctly at 100 kHz, but disappears from the I2C scanner at 400 kHz after two more modules and 30 cm of jumper wire are added. What should be checked first?

AInspect the cloud endpoint instead of the physical I2C bus.

BInspect bus capacitance, pull-ups, and rise time at 400 kHz.

CInspect the address because an address collision explains the failures after the I2C speed change.

DInspect SPI chip-select because its selection signal governs the device's response on the shared wires.

Show answer

Answer: B Adding devices and wire increases capacitance.

Print reference

Answers

Answer key.

A · For a normal 7-bit addressed transfer, bits [7:1] carry 0x76 and bit 0 selects write (0) or read (1).
A · The receiver pulls SDA low to confirm that the preceding byte was accepted.
A · I2C sends the 7-bit address in bits 7 through 1 of the first byte.
B · Adding devices and wire increases capacitance.