IoT Fundamentals · Study deck
Sampling and Aliasing
Picture a pressure sensor whose stored values flatten near the top of its range.
Physics Phoebe is your guide for this deck.
After studying this chapter
Learning objectives
You will be able to:
- Explain: Signal bandwidth drives the sample-rate and anti-alias plan; sensor accuracy and noise decide whether extra bits are useful; power budget constrains whether a faster or higher-resolution converter is practical for a battery device.
- Explain: The dashboard may only need one pressure value each second, but the ADC path still needs to preserve pump ripple, cavitation pulses, and mains-coupled noise before the firmware decides what to summarize.
- Explain: The record matters because a sample rate that made sense in the lab can become wrong after a sensor, filter, enclosure, timer, or power rail changes.
Major section
In 60 Seconds
More samples cannot repair a signal that the input stage has already clipped.
- An analog-to-digital converter means the part that turns a changing voltage into numbers.
- ADC is the short name used here.
- An ADC makes a timed digital record of a changing analog voltage.
Major section
What the ADC Promises
An analog-to-digital converter, or ADC, is the snapshot gate between the physical world and the firmware record.
- The ADC samples that voltage at scheduled moments and stores each result as a number.
- If you take too few photos, the same wheel can look slower, stopped, or even reversed.
- That false motion is aliasing.
Major section
What the ADC Promises (continued)
A vibration monitor may need hundreds or thousands of readings per second because the useful fault pattern changes quickly.
- The important idea is not "sample as fast as possible." The important idea is trust: a digital sample should still mean the physical thing it claims to mean.
- In ADC work, aliasing can turn high-frequency vibration, electrical noise, or switching ripple into a believable low-frequency pattern.
- More digits can still describe the wrong waveform.
Major section
What the ADC Promises (continued)
For example, an irrigation pump monitor might use a 0.5 V to 4.5 V pressure transducer on an STM32 or ESP32 SAR ADC.
- The dashboard may only need one pressure value each second, but the ADC path still needs to preserve pump ripple, cavitation pulses, and mains-coupled noise before the firmware decides what to summarize.
- If the firmware sampled once per second directly, the data table would still fill with numbers, but a fast pressure pulse or electrical ripple could fold into a false slow drift.
- A higher-resolution ADC does not fix a wrong sample rate.
Major section
Apply It: Build the ADC Sample Plan
The practical ADC workflow starts with the signal requirement and ends with a short review record.
- Walkthrough: From Sensor Voltage to Digital Evidence State the measurement.: Name the physical quantity, expected range, fastest useful change, and acceptable delay.
- Digital filters cannot reliably remove content after it has folded into the sampled band.
Major section
Apply It: Build the ADC Sample Plan (continued)
A 12-bit ADC using a 3.3 V reference has 4096 possible codes.
- Condition the voltage.: Scale or shift the sensor output so it fits the ADC input range without clipping or wasting most codes.
- An ADC selection guide keeps three reviews separate.
- The team can reproduce the voltage-to-temperature conversion later.
Major section
Apply It: Build the ADC Sample Plan (continued)
The sensor uses about half the ADC input range, so there is useful but not perfect code coverage.
- Validate and record.: Use a known input, reference capture, or repeatable field test to prove the code record still maps to the physical signal.
- The upper questions explain these differences; extra converter bits are useful only when the sensor and noise level justify them.
- Each count is about 0.08 degrees C for this sensor scale.
Major section
Apply It: Build the ADC Sample Plan (continued)
Signal bandwidth drives the sample-rate and anti-alias plan; sensor accuracy and noise decide whether extra bits are useful; power budget constrains whether a faster or higher-resolution converter is practical for a battery device.
- The pair turns Nyquist decision map: useful bandwidth, filter cutoff, transition margin, and selected sample rate into something the team can verify.
- Temperature usually changes slowly, but airflow, heater cycling, or diagnostics may set the real sample need.
- The calculation says the ADC has enough amplitude detail for many temperature tasks.
Major section
Apply It: Build the ADC Sample Plan (continued)
Incremental Practice Beginner For a slowly changing environment reading, justify why a low sample rate still preserves the useful signal.
- Intermediate For a vibration signal up to 40 Hz, record why the mathematical lower boundary is above 80 samples/s and why the real design needs more margin.
- Advanced Inject a known high-frequency component before the ADC and verify that the analog filter keeps it from folding into the band of interest.
- If your job is to choose a defensible sample rate and record why it works, you can stop here.
Major section
Apply It: Build the ADC Sample Plan (continued)
The sample plan is incomplete until voltage resolution, input noise, sensor sensitivity, and observation time are read from the same ledger.
- The visible gain in effective bits is purchased with a longer acquisition window; nominal ADC width has not changed.
- A design that reports the smaller uncertainty but omits the longer observation time has described only half of the trade-off.
- The record matters because a sample rate that made sense in the lab can become wrong after a sensor, filter, enclosure, timer, or power rail changes.
Major section
Under the Hood: Math, Limits, and Failure Modes
The deeper layer explains why the practitioner workflow separates sampling, filtering, resolution, and evidence.
- This boundary assumes the signal above the useful band has been removed before sampling.
- Real anti-alias filters have transition bands.
- A practical design usually samples faster than the bare minimum so the filter has room to attenuate unwanted content.
Major section
Under the Hood: Math, Limits, and Failure Modes (continued)
Two different high-frequency components can fold into the same apparent low-frequency band, which makes post-processing ambiguous.
- The middle panel shows how insufficient sampling turns the original signal into a false lower-frequency pattern.
- The ideal quantization error is within plus or minus half an LSB.
- For a 12-bit, 3.3 V ADC, one LSB is about 0.806 mV, so the ideal quantization uncertainty is about +/-0.403 mV.
Major section
Sammy's Math Bridge: Time and Voltage Resolution
The mathematical gist.: A 40 Hz signal needs at least 80 samples/s before filter margin, while 90 Hz sampled at 100 samples/s folds to 10 Hz.
- Sampling rate protects the time axis; bit depth divides the voltage axis.
Major section
Summary
ADC design starts with the signal requirement, not the fastest available sample rate.
- Nyquist gives a lower boundary, while real designs need filter and implementation margin.
- Aliasing creates false patterns that can survive into dashboards and analytics.
- A review record keeps the design reproducible when sensors, firmware, filters, or deployment conditions change.
Deck summary
Key takeaways
More samples cannot repair a signal that the input stage has already clipped.
- An analog-to-digital converter, or ADC, is the snapshot gate between the physical world and the firmware record.
- A vibration monitor may need hundreds or thousands of readings per second because the useful fault pattern changes quickly.
- For example, an irrigation pump monitor might use a 0.5 V to 4.5 V pressure transducer on an STM32 or ESP32 SAR ADC.
- The practical ADC workflow starts with the signal requirement and ends with a short review record.
Retrieval practice
Recall check 1 of 3
Physics Phoebe says: answer from memory, then check your reasoning.
Q1A sensor trace shows a slow wave, but the slow wave disappears when the sample rate changes. What is the first ADC issue to review?
Show answer
Answer: C A pattern that moves when the sample rate changes is a strong aliasing warning.
Retrieval practice
Recall check 2 of 3
Physics Phoebe says: answer from memory, then check your reasoning.
Q2A team needs to preserve a signal component up to 40 Hz. Which review note is strongest?
Show answer
Answer: A The two-times rule is only the lower boundary; the review also needs anti-alias filter evidence and practical margin for rolloff and timing tolerance.
Retrieval practice
Recall check 3 of 3
Physics Phoebe says: answer from memory, then check your reasoning.
Q3A 1200 Hz signal reaches an ADC sampled at 1000 samples/s. What apparent frequency can it fold to?
Show answer
Answer: A The nearest sample-rate multiple is 1000 Hz, so the folded component is |1200 - 1000| = 200 Hz.
Print reference
Answers
Answer key.
- C · A pattern that moves when the sample rate changes is a strong aliasing warning.
- A · The two-times rule is only the lower boundary; the review also needs anti-alias filter evidence and practical margin for rolloff and timing tolerance.
- A · The nearest sample-rate multiple is 1000 Hz, so the folded component is |1200 - 1000| = 200 Hz.