Energy & Power · Study deck

Hardware Optimization Strategies

Picture a battery sensor that wakes, reads a value, sends it, and sleeps.

Battery Bruno is your guide for this deck.

optimizationhardware

Battery Bruno, the module guide, in a scene from this chapter.

After studying this chapter

Learning objectives

You will be able to:

Compare general-purpose processors, hardware peripherals, DSP-style blocks, reconfigurable logic, and custom silicon.
Explain why data movement and memory bandwidth can dominate hardware optimization.
Use selection gates for acceleration, power domains, clocks, and platform changes.
Identify when a hardware change is premature or too risky.

Major section

Start With the Block That Burns Energy

One part may use most of the energy.

It may be the radio, a memory copy, a voltage converter, or a block that never turns off.
A faster chip is not an answer by itself.
A special block can finish work quickly but waste power while idle.

Major section

Start With the Block That Burns Energy (continued)

A wider data path can save time but add cost and design risk.

A new power part can lose its gain at light load.
The simple cycle cannot pick a processor, memory path, power rail, or custom chip.
It also cannot prove heat, update, or supply risk.

Major section

Start With the Block That Burns Energy (continued)

A hardware optimization is useful only when it reduces the part of the workload that dominates the budget.

Those choices need real loads and a before-and-after test on the whole device.
The deeper checks explain when the simple rule holds and when a trade-off changes the result.
An accelerator, buck regulator, DMA path, or peripheral choice can save energy, but it can also add idle loss and integration cost.

Real photograph of shunt resistor (current-sense)

Major section

Hardware Choices As A Spectrum

Moving right can turn a stable kernel into dedicated parallel hardware, but each step gives up some ability to repair changing requirements in software.

An ASIC reaches the highest performance and volume efficiency only after accepting fixed function and potentially very high design cost.
Most flexible, but repeated numeric or transfer-heavy work can waste energy.

Hardware optimization spectrum from general processor to peripheral offload, DSP-style accelerator, reconfigurable logic, and custom silicon.

Major section

Selection Gates

In the first panel the workload is held steady while the real limit is measured.

The last panel compares before and after gauges for time, energy, and correct results.
That sequence leads into the six-gate diagram below: a fast chip is useful only when the full system passes those checks.

Hardware selection gates showing workload stability, measured bottleneck, data movement, update need, volume/risk, and validation evidence.

Major section

Data Movement And Memory

A fast accelerator that requires repeated copies, cache flushes, wakeups, or polling can lose the energy benefit.

The useful question is not merely how quickly the accelerator runs, but how much of the route can complete while the CPU remains asleep.

Data movement path showing sensor, peripheral buffer, DMA, memory bank, accelerator, CPU, and sleep opportunity.

Major section

Power Domains, Clocks, And Peripherals

Hardware optimization also includes turning hardware off correctly.

Peripheral state may be lost or reads may fail when a clock is off.
Lower speed may increase active time or break communication timing.

A power-supply path is an optimization choice: protection, regulation, filtering, and load distribution all determine whether voltage headroom becomes useful work or heat.

Major section

Worked Review: Streaming Sensor Node

High-priority candidate because it can create sleep time.

A software-only prototype works, but the energy trace shows the CPU stays awake while it copies samples and waits for transfers.
CPU waits during sample transfer.
Batch events and use a low-power wake source for threshold detection.

Major section

How You Make The Rail Decides How Much You Waste

The regulator topology becomes a physical heat and headroom choice at the component.

In Figure: A power-supply path is an optimization choice, the source column spans a 3.7 V LiPo, 5 V USB, higher-voltage solar input, and a 12 V adapter, so no single regulator topology fits every case.

A 78xx linear regulator is the physical version of the simple LDO-side tradeoff: three pins make it easy to use, but the voltage it drops is dissipated as heat rather than converted efficiently. Photo: Retired electrician, CC0

Major section

ASIC Specialization Axes

Cache choices are equally application-specific: a streaming kernel may benefit more from scratchpad DMA than from a large associative cache whose tags and replacement logic switch on every access.

Instruction fusion shows how the axes interact.
Otherwise, the “special” instruction waits on memory or forces marshaling that consumes the saving.
Memory banking has the same dependency.

Major section

ASIC Specialization Axes (continued)

Replacing load, multiply, add, store with a fused kernel only saves energy if operands arrive without extra copies, the accumulator width preserves accuracy, the register file can supply the ports, and the compiler recognizes the pattern.

Four single-ported banks can serve four simultaneous accesses only when addresses distribute across different banks.
Profiling must therefore record access strides and conflicts, not just total bytes.
The exit criterion is a four-column ledger—performance, energy, area, and toolchain consequence—for every proposed feature.
Specialize only when the evidence shows a stable benefit across representative and worst-case workloads.

Five evidence-driven ASIC specialization lanes.

Major section

Heterogeneous Run-State Migration

Heterogeneous multicore systems can implement the same instruction architecture on “little” efficient cores and “big” fast cores.

Compatibility lets a thread migrate, but migration is not free: caches may be cold, state must be transferred, and the receiving core may need a voltage or frequency transition.
A big core can consume more power yet less energy if its shorter runtime is enough to overcome transition and refill costs.
Conversely, bouncing a short task between cores can cost more than simply finishing it where it started.
Practical schedulers therefore use utilization windows or hysteresis instead of migrating on every brief load spike.

Major section

Always-On Vision Accelerator Data Path

In the chapter’s illustrative 20:1 feature-compression model, the transferred representation is about 20 times smaller than the raw pixel stream.

The important result is not the portrait of a detection chip; it is the boundary change from pixel-space transmission to feature-space transmission.
The accelerator is worthwhile only when its extraction energy plus feature-transfer energy is below the raw-transfer and downstream-processing energy it replaces.
If feature extraction reduces the representation by factor $r$ , then $D_{feature}=D_{raw}/r$ .

Always-on vision compute and data-movement energy.

Deck summary

Key takeaways

One part may use most of the energy.

A wider data path can save time but add cost and design risk.
A hardware optimization is useful only when it reduces the part of the workload that dominates the budget.
Moving right can turn a stable kernel into dedicated parallel hardware, but each step gives up some ability to repair changing requirements in software.
In the first panel the workload is held steady while the real limit is measured.

Retrieval practice

Recall check 1 of 5

Battery Bruno says: answer from memory, then check your reasoning.

Q1A sensor node keeps the CPU awake while moving samples from a peripheral into memory. The compute step is not yet the dominant energy contributor. Which hardware optimization should be investigated first?

AMove to custom silicon before measuring transfer-state energy.

BOptimize filtering because its computation accounts for the measured CPU wait.

CUse DMA or buffering so the CPU can sleep during transfers.

DRaise clock speed to move peripheral samples more quickly.

Show answer

Answer: C Hardware optimization should address the measured limiter.

Retrieval practice

Recall check 2 of 5

Battery Bruno says: answer from memory, then check your reasoning.

Q2A team wants a fixed-function accelerator for an algorithm that is still changing every sprint. What is the strongest concern?

AAn accelerator necessarily uses more charge than equivalent software.

BHardware determinism removes the need to validate changing behavior.

CA fixed accelerator may freeze product behavior before the algorithm stabilizes.

DDocumentation style is the main concern as the algorithm evolves.

Show answer

Answer: C Workload stability is a key gate for hardware specialization.

Q3What measured compute, memory, transfer or energy limit reveals where acceleration could help?

ARepresentative Demand

BBottleneck

CHardware path

DValidation

Show answer

Answer: B The bottleneck belongs beside workload evidence because measured compute, memory, transfer, or energy limits identify what acceleration could help.

Retrieval practice

Recall check 3 of 5

Battery Bruno says: answer from memory, then check your reasoning.

Q4An LDO produces a 3.3 V rail from a 4.2 V battery while supplying 100 mA. Roughly what is its efficiency and where does the lost energy go?

AAbout 100%, because the output and battery currents match.

BAbout 127%, because 4.2/3.3 is the voltage ratio.

CAbout 79%, with the voltage drop dissipated as heat in the LDO.

DAbout 79%, with the lost energy returned to the battery.

Show answer

Answer: C An LDO's efficiency is about Vout/Vin = 3.3/4.2 = 79%. It drops 0.9 V at 100 mA, so about 90 mW becomes heat.

Retrieval practice

Recall check 4 of 5

Battery Bruno says: answer from memory, then check your reasoning.

Q5A 90% buck and an LDO both make 3.3 V for a 100 mA (330 mW) load from a 4.2 V battery. How much battery current does each draw?

ABoth draw 100 mA because the downstream load takes 100 mA.

BLDO draws 100 mA; 90%-efficient buck draws about 87 mA.

CBuck draws about 110 mA because switching wastes charge.

DLDO draws about 79 mA because its efficiency changes input current.

Show answer

Answer: B The LDO passes the full 100 mA.

Retrieval practice

Recall check 5 of 5

Battery Bruno says: answer from memory, then check your reasoning.

Q6A node uses a buck that is 90% efficient at its active load. It sleeps 99% of the time at a 10 uA load; in sleep, the measured buck input is 25 uA including 15 uA quiescent current, while a candidate LDO draws 11 uA including 1 uA quiescent current. Why might the LDO give longer battery life overall?

ABuck draws 25 µA in dominant sleep; LDO needs only 11 µA.

BBuck efficiency is below LDO efficiency at every possible load.

CChoose LDO because its conversion efficiency exceeds buck conversion at the active duty cycle.

DQuiescent regulator draw has no effect on battery lifetime.

Show answer

Answer: A Efficiency is load-dependent.

Print reference

Answers

Answer key.

C · Hardware optimization should address the measured limiter.
C · Workload stability is a key gate for hardware specialization.
B · The bottleneck belongs beside workload evidence because measured compute, memory, transfer, or energy limits identify what acceleration could help.
C · An LDO's efficiency is about Vout/Vin = 3.3/4.2 = 79%. It drops 0.9 V at 100 mA, so about 90 mW becomes heat.
B · The LDO passes the full 100 mA.
A · Efficiency is load-dependent.