Energy & Power · Study deck

Hardware Optimization Strategies

Picture a battery sensor that wakes, reads a value, sends it, and sleeps.

Battery Bruno is your guide for this deck.

optimizationhardware

Battery Bruno, the module guide, in a scene from this chapter.

After studying this chapter

Learning objectives

You will be able to:

Compare general-purpose processors, hardware peripherals, DSP-style blocks, reconfigurable logic, and custom silicon.
Explain why data movement and memory bandwidth can dominate hardware optimization.
Use selection gates for acceleration, power domains, clocks, and platform changes.
Identify when a hardware change is premature or too risky.

Major section

Start With the Block That Burns Energy

One part may use most of the energy.

It may be the radio, a memory copy, a voltage converter, or a block that never turns off.
A faster chip is not an answer by itself.
A special block can finish work quickly but waste power while idle.

Major section

Start With the Block That Burns Energy (continued)

A wider data path can save time but add cost and design risk.

A new power part can lose its gain at light load.
The simple cycle cannot pick a processor, memory path, power rail, or custom chip.
It also cannot prove heat, update, or supply risk.

Major section

Start With the Block That Burns Energy (continued)

A hardware optimization is useful only when it reduces the part of the workload that dominates the budget.

Those choices need real loads and a before-and-after test on the whole device.
The deeper checks explain when the simple rule holds and when a trade-off changes the result.
An accelerator, buck regulator, DMA path, or peripheral choice can save energy, but it can also add idle loss and integration cost.

Major section

Hardware Choices As A Spectrum

Moving right can turn a stable kernel into dedicated parallel hardware, but each step gives up some ability to repair changing requirements in software.

An ASIC reaches the highest performance and volume efficiency only after accepting fixed function and potentially very high design cost.
Most flexible, but repeated numeric or transfer-heavy work can waste energy.

Hardware optimization spectrum from general processor to peripheral offload, DSP-style accelerator, reconfigurable logic, and custom silicon.

Major section

Selection Gates

The third then asks whether the proposed data path avoids copies and wakeups; a fast kernel behind an expensive transfer can lose at system level.

Workload stability: The algorithm, data size, and accuracy target should be stable before hardware is specialized.

Hardware selection gates showing workload stability, measured bottleneck, data movement, update need, volume/risk, and validation evidence.

Major section

Data Movement And Memory

A fast accelerator that requires repeated copies, cache flushes, wakeups, or polling can lose the energy benefit.

The useful question is not merely how quickly the accelerator runs, but how much of the route can complete while the CPU remains asleep.

Data movement path showing sensor, peripheral buffer, DMA, memory bank, accelerator, CPU, and sleep opportunity.

Major section

Worked Review: Streaming Sensor Node

High-priority candidate because it can create sleep time.

A software-only prototype works, but the energy trace shows the CPU stays awake while it copies samples and waits for transfers.
CPU waits during sample transfer.
Batch events and use a low-power wake source for threshold detection.

Major section

How You Make The Rail Decides How Much You Waste

The regulator topology becomes a physical heat and headroom choice at the component.

In Figure: A power-supply path is an optimization choice, the source column spans a 3.7 V LiPo, 5 V USB, higher-voltage solar input, and a 12 V adapter, so no single regulator topology fits every case.

A 78xx linear regulator is the physical version of the simple LDO-side tradeoff: three pins make it easy to use, but the voltage it drops is dissipated as heat rather than converted efficiently. Photo: Retired electrician, CC0

Major section

ASIC Specialization Axes

Cache choices are equally application-specific: a streaming kernel may benefit more from scratchpad DMA than from a large associative cache whose tags and replacement logic switch on every access.

Instruction fusion shows how the axes interact.
Otherwise, the “special” instruction waits on memory or forces marshaling that consumes the saving.
Memory banking has the same dependency.

Major section

ASIC Specialization Axes (continued)

Replacing load, multiply, add, store with a fused kernel only saves energy if operands arrive without extra copies, the accumulator width preserves accuracy, the register file can supply the ports, and the compiler recognizes the pattern.

Four single-ported banks can serve four simultaneous accesses only when addresses distribute across different banks.
Profiling must therefore record access strides and conflicts, not just total bytes.
The exit criterion is a four-column ledger—performance, energy, area, and toolchain consequence—for every proposed feature.
Specialize only when the evidence shows a stable benefit across representative and worst-case workloads.

Major section

Heterogeneous Run-State Migration

Heterogeneous multicore systems can implement the same instruction architecture on “little” efficient cores and “big” fast cores.

Compatibility lets a thread migrate, but migration is not free: caches may be cold, state must be transferred, and the receiving core may need a voltage or frequency transition.
A big core can consume more power yet less energy if its shorter runtime is enough to overcome transition and refill costs.
Conversely, bouncing a short task between cores can cost more than simply finishing it where it started.
Practical schedulers therefore use utilization windows or hysteresis instead of migrating on every brief load spike.

Major section

Always-On Vision Accelerator Data Path

The important result is not the portrait of a detection chip; it is the boundary change from pixel-space transmission to feature-space transmission.

The accelerator is worthwhile only when its extraction energy plus feature-transfer energy is below the raw-transfer and downstream-processing energy it replaces.
The review must also test whether the chosen features preserve required accuracy, whether the feature format can evolve with the model, and whether keeping the detector off-chip creates a privacy or availability risk.
If feature extraction reduces the representation by factor $r$, then $D_{feature}=D_{raw}/r$.

Deck summary

Key takeaways

One part may use most of the energy.

A wider data path can save time but add cost and design risk.
A hardware optimization is useful only when it reduces the part of the workload that dominates the budget.
Moving right can turn a stable kernel into dedicated parallel hardware, but each step gives up some ability to repair changing requirements in software.
The third then asks whether the proposed data path avoids copies and wakeups; a fast kernel behind an expensive transfer can lose at system level.

Retrieval practice

Recall check 1 of 6

Battery Bruno says: answer from memory, then check your reasoning.

Q1A sensor node keeps the CPU awake while moving samples from a peripheral into memory. The compute step is not yet the dominant energy contributor. Which hardware optimization should be investigated first?

AMove the entire product to custom silicon immediately

BUse peripheral buffering or DMA so the CPU can sleep during transfers

COptimize the filtering algorithm so processing completes sooner and frees more time for sleep

DIncrease clock speed so sample transfers complete sooner

Show answer

Answer: B Hardware optimization should address the measured limiter.

Retrieval practice

Recall check 2 of 6

Battery Bruno says: answer from memory, then check your reasoning.

Q2A team wants a fixed-function accelerator for an algorithm that is still changing every sprint. What is the strongest concern?

AThe accelerator may lock the product into behavior that is not stable yet

BThe accelerator will always use more energy than software

CThe team should ignore validation because hardware is deterministic

DThe only issue is documentation style

Show answer

Answer: A Workload stability is a key gate for hardware specialization.

Retrieval practice

Recall check 3 of 6

Battery Bruno says: answer from memory, then check your reasoning.

Q3Place each hardware optimization artifact where it lives so you can choose acceleration for a measured limiter and still protect whole-system behavior.

ARepresentative Demand

BBottleneck

CHardware path

DValidation

Show answer

Answer: A Move from representative demand and a measured limiter to a justified hardware path, then remeasure the integrated system so you can avoid acceleration that merely moves the bottleneck.

Retrieval practice

Recall check 4 of 6

Battery Bruno says: answer from memory, then check your reasoning.

Q4An LDO produces a 3.3 V rail from a 4.2 V battery while supplying 100 mA. Roughly what is its efficiency and where does the lost energy go?

AAbout 100%, because the output and battery currents match.

BAbout 127%, because 4.2/3.3 is the voltage ratio.

CAbout 79%, with the voltage drop dissipated as heat in the LDO.

DAbout 79%, with the lost energy returned to the battery.

Show answer

Answer: C An LDO's efficiency is about Vout/Vin = 3.3/4.2 = 79%. It drops 0.9 V at 100 mA, so about 90 mW becomes heat.

Retrieval practice

Recall check 5 of 6

Battery Bruno says: answer from memory, then check your reasoning.

Q5A 90% buck and an LDO both make 3.3 V for a 100 mA (330 mW) load from a 4.2 V battery. How much battery current does each draw?

AThe LDO draws 100 mA; the buck draws about 87 mA.

BBoth draw 100 mA, because the load is 100 mA.

CThe buck draws more, about 110 mA, because switching is wasteful.

DThe LDO draws about 79 mA due to its efficiency.

Show answer

Answer: A The LDO passes the full 100 mA.

Retrieval practice

Recall check 6 of 6

Battery Bruno says: answer from memory, then check your reasoning.

Q6A node uses one 90%-efficient buck for everything. It sleeps 99% of the time at a 10 uA load, but the buck's quiescent current is 15 uA. Why might a low-quiescent LDO give longer battery life overall?

ADuring the dominant sleep time the buck draws 25 uA to deliver 10 uA

BThe buck is less efficient than the LDO at every load.

CLDOs always beat bucks regardless of load.

DQuiescent current does not affect battery life.

Show answer

Answer: A Efficiency is load-dependent.

Print reference

Answers 1 of 2

Answer key.

B · Hardware optimization should address the measured limiter.
A · Workload stability is a key gate for hardware specialization.
A · Move from representative demand and a measured limiter to a justified hardware path, then remeasure the integrated system so you can avoid acceleration that merely moves the bottleneck.
C · An LDO's efficiency is about Vout/Vin = 3.3/4.2 = 79%. It drops 0.9 V at 100 mA, so about 90 mW becomes heat.

Print reference

Answers 2 of 2

Answer key.

A · The LDO passes the full 100 mA.
A · Efficiency is load-dependent.