Reference Architectures · Study deck

Power and Interfaces: Decision Records

A valve node must wake, sample, decide, and drive its load before its deadline.

Blueprint Bina is your guide for this deck.

hardwarecharpower

Blueprint Bina, the module guide, in a scene from this chapter.

After studying this chapter

Learning objectives

You will be able to:

build a power-state ledger for boot, active work, idle wait, sleep, fault, service, and update modes;
connect wake sources, retained data, and safe output states to the device mission;
select GPIO, ADC, PWM, I2C, SPI, or UART based on signal measurements rather than habit;
identify voltage-domain, pull-up, debounce, level-shift, and protection needs at each boundary;

Major section

Start With the Battery and Port

The design can fail even when every part works alone.

The signal level, wire rule, power draw, and safe output all have to agree.
A microcontroller means the small computer inside the box.
GPIO means general purpose input and output pins.
An actuator means a part that creates a physical action.

Major section

Start With the Battery and Port (continued)

An analog-to-digital converter means a circuit that turns a voltage into a number; it is called an ADC.

Pulse-width modulation means control made by changing how long a signal stays on; it is called PWM.
Reverse a lead, lower the battery, hold the data line, repeat a command, and restart the controller.
The valve must return to a named safe state.
This runway does not select a board or size every component.

Major section

Phoebe's Field Notes: Why "The Reference And Divider Settle" Is A Real Deadline

The mathematical gist.: A 12-bit, 3.3 V ADC has $2^{12}=4096$ codes, so one step is $3.3/4096=0.806$ mV and the ideal quantisation SNR is 74.0 dB.

More bits cannot repair a voltage sampled before it settles.

Major section

State Ledger

A power design is traceable only when every state has a name, entry condition, exit condition, draw estimate, retained data, and output rule.

The device starts clocks, memory, peripherals, and output defaults.
Outputs should remain safe until firmware explicitly owns them.
The device samples, computes, drives actuators, writes state, or transmits.
This state should be short and bounded.

Power-state ledger showing boot, active work, idle wait, sleep or retention, fault, service, and update states with entry rule, wake source, retained data, safe output, and measurement proof.

Major section

Wake and Retention Plan

Sleep is useful only when the device can wake for the right reason and recover enough state to act correctly.

Between them, the wake and retention plan relationship becomes visible: Deep Sleep vs Light Sleep Comparison.

Major section

Cortex-M Core Options and Portability

“Cortex-M” identifies a processor-core family, not a complete microcontroller.

That boundary explains both the family's strong compiler portability and the real cost of moving firmware between chips.
Later Cortex-M cores also use Armv8-M and newer profiles, so never infer the architecture from the letter “M” alone.

Microcontroller interface ownership connects the processing unit to analogue inputs, GPIO, serial buses, USB, and driven outputs, each with its own electrical and firmware boundary.

Major section

Signal Boundaries

Signal compatibility is a boundary decision.

Establish the voltage domain across normal, boot, sleep, service, and fault states, then record the line's pull behavior: pulled high, pulled low, actively driven, tri-stated, or held externally.
Where logic ranges differ, choose the appropriate level shifter, divider, isolator, or open-drain arrangement rather than treating connector compatibility as electrical compatibility.

Signal boundary check showing voltage domain, pull behavior, level shift, driver stage, analog filter, connector protection, and back-feed prevention.

Major section

Signal Boundaries (continued)

A signal is not approved just because the connector fits.

A GPIO that reaches a high-load actuator needs a driver stage plus flyback or transient protection; an ADC input needs evidence for source impedance, reference rail, filtering, and sample timing.
Finish by testing the powered-off state so an energized peripheral cannot back-feed the controller through a signal pin.
This sequence turns the boundary from a parts list into a set of states the design can prove.

Deck summary

Key takeaways

The design can fail even when every part works alone.

An analog-to-digital converter means a circuit that turns a voltage into a number; it is called an ADC.
The mathematical gist.: A 12-bit, 3.3 V ADC has $2^{12}=4096$ codes, so one step is $3.3/4096=0.806$ mV and the ideal quantisation SNR is 74.0 dB.
A power design is traceable only when every state has a name, entry condition, exit condition, draw estimate, retained data, and output rule.
Sleep is useful only when the device can wake for the right reason and recover enough state to act correctly.

Retrieval practice

Recall check

Blueprint Bina says: answer from memory, then check your reasoning.

Q1A remote valve node sleeps between reports, must wake on a leak input, keep the valve driver safe during reset, sample ADC feedback, and expose a service UART. Which first check keeps the hardware boundary choice traceable?

AApprove the battery size first because extra capacity covers wake, valve movement, sampling, radio bursts, and service sessions.

BAccept the pin table first because spare GPIO, ADC, SPI, and UART labels prove safe electrical boundaries.

CRecord sleep rail, leak level, pull method, wake latency, valve default, ADC range, burst draw, service timeout, and review conditions.

DUse the active bench demo first because one leak test proves sleep, reset, bus recovery, and service behavior.

Show answer

Answer: C A traceable power and interface decision proves the retained wake path, safe output defaults, signal limits, measured bursts, service behavior, and review conditions before the device depends on that hardware boundary.

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Answers

Answer key.

C · A traceable power and interface decision proves the retained wake path, safe output defaults, signal limits, measured bursts, service behavior, and review conditions before the device depends on that hardware boundary.