Reference Architectures · Study deck

Power and Interfaces: Decision Records

A valve node must wake, sample, decide, and drive its load before its deadline.

Blueprint Bina is your guide for this deck.

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Blueprint Bina, the module guide, in a scene from this chapter.

After studying this chapter

Learning objectives

You will be able to:

build a power-state ledger for boot, active work, idle wait, sleep, fault, service, and update modes;
connect wake sources, retained data, and safe output states to the device mission;
select GPIO, ADC, PWM, I2C, SPI, or UART based on signal measurements rather than habit;
identify voltage-domain, pull-up, debounce, level-shift, and protection needs at each boundary;

Power and interface decision route from device mission to state ledger, wake plan, signal map, boundary protection, measurements, and decision record.

Major section

Start With the Battery and Port

The design can fail even when every part works alone.

The signal level, wire rule, power draw, and safe output all have to agree.
A microcontroller means the small computer inside the box.
GPIO means general purpose input and output pins.
An actuator means a part that creates a physical action.

Major section

Start With the Battery and Port (continued)

An analog-to-digital converter means a circuit that turns a voltage into a number; it is called an ADC.

Pulse-width modulation means control made by changing how long a signal stays on; it is called PWM.
Reverse a lead, lower the battery, hold the data line, repeat a command, and restart the controller.
The valve must return to a named safe state.
This runway does not select a board or size every component.

Major section

Phoebe's Field Notes: Why "The Reference And Divider Settle" Is A Real Deadline

The mathematical gist: A 12-bit, 3.3 V ADC has $2^{12}=4096$ codes, so one step is $3.3/4096=0.806$ mV and the ideal quantisation SNR is 74.0 dB.

More bits cannot repair a voltage sampled before it settles.

Major section

State Ledger

A power design is traceable only when every state has a name, entry condition, exit condition, draw estimate, retained data, and output rule.

The device starts clocks, memory, peripherals, and output defaults.
Outputs should remain safe until firmware explicitly owns them.
The device samples, computes, drives actuators, writes state, or transmits.
This state should be short and bounded.

Power-state ledger lists boot, active, idle, sleep, fault, service and update states with entry, exit, wake, retained data and safe-output columns.

Major section

Wake and Retention Plan

Sleep is useful only when the device can wake for the right reason and recover enough state to act correctly.

Deep sleep reaches roughly 50–500 µA, or 0.05–0.5 mA, but trades that saving for slower wake and less retained context.

Sleep-mode comparison lists active, light and deep sleep power, retention and wake behavior. A worked interval calculation compares 0.8 mA light sleep with 10 µA deep sleep plus boot cost: light wins at five-second wakes, deep sleep at sixty-second wakes. — Deep Sleep vs Light Sleep Comparison

Major section

Cortex-M Core Options and Portability

“Cortex-M” identifies a processor-core family, not a complete microcontroller.

That boundary explains both the family's strong compiler portability and the real cost of moving firmware between chips.
Later Cortex-M cores also use Armv8-M and newer profiles, so never infer the architecture from the letter “M” alone.

Microcontroller interface map connects an analog sensor to ADC, a higher-rate peripheral to SPI, and GPIO through a driver to a load. It calls for range, timing, boot-default and bus-sharing evidence before approving those boundaries.

Major section

Cortex-M Core Options and Portability (continued)

The compiler may accept the same application source, and the scheduler may keep the same task model.

The I2C temperature driver still has to be rebound to different clock gates, pins, status flags, and recovery semantics.
An ADC input needs a known voltage range, reference, source impedance, filter, and sample time; extra bits cannot rescue a reading taken before it settles.
GPIO can command a driver for a valve, but the high load needs its own power path and protection.
SPI needs clock mode, chip-select ownership, and sharing checks, while I2C needs a pull-up rail and stuck-bus recovery.

Major section

Signal Boundaries

Signal compatibility is a boundary decision.

Establish the voltage domain across normal, boot, sleep, service, and fault states, then record the line's pull behavior: pulled high, pulled low, actively driven, tri-stated, or held externally.
Where logic ranges differ, choose the appropriate level shifter, divider, isolator, or open-drain arrangement rather than treating connector compatibility as electrical compatibility.

Signal boundary check shows controller and external voltage domains, defined pulls, level shift, driver stage, filtering and protection. It asks for range, idle level, power-off behavior and recovery evidence.

Major section

Signal Boundaries (continued)

A signal is not approved just because the connector fits.

A GPIO that reaches a high-load actuator needs a driver stage plus flyback or transient protection; an ADC input needs evidence for source impedance, reference rail, filtering, and sample timing.
Finish by testing the powered-off state so an energized peripheral cannot back-feed the controller through a signal pin.
This sequence turns the boundary from a parts list into a set of states the design can prove.

Deck summary

Key takeaways

The design can fail even when every part works alone.

An analog-to-digital converter means a circuit that turns a voltage into a number; it is called an ADC.
The mathematical gist: A 12-bit, 3.3 V ADC has $2^{12}=4096$ codes, so one step is $3.3/4096=0.806$ mV and the ideal quantisation SNR is 74.0 dB.
A power design is traceable only when every state has a name, entry condition, exit condition, draw estimate, retained data, and output rule.
Sleep is useful only when the device can wake for the right reason and recover enough state to act correctly.

Retrieval practice

Recall check 1 of 3

Blueprint Bina says: answer from memory, then check your reasoning.

Q1A remote valve node sleeps between reports, must wake on a leak input, keep the valve driver safe during reset, sample ADC feedback, and expose a service UART. Which first check keeps the hardware boundary choice traceable?

AApprove the battery size first because extra capacity covers wake, valve movement, sampling, radio bursts, and service sessions.

BAccept the pin table first because spare GPIO, ADC, SPI, and UART labels prove safe electrical boundaries.

CUse the active bench demo first because one leak test proves sleep, reset, bus recovery, and service behavior.

DRecord sleep rail, leak level, pull method, wake latency, valve default, ADC range, burst draw, timeout and review conditions.

Show answer

Answer: D A traceable power and interface decision proves the retained wake path, safe output defaults, signal limits, measured bursts, service behavior, and review conditions before the device depends on that hardware boundary.

Retrieval practice

Recall check 2 of 3

Blueprint Bina says: answer from memory, then check your reasoning.

Q2A valve-node interface works on the bench. What record makes its field choice testable and serviceable?

AKeep pin list alone, omitting safe states, fault tests, and service owner.

BKeep only the successful bench photo without field fault evidence.

CLeave interface owner and retest trigger for future repair staff.

DName signal owner, safe states, limits, tests, rejected paths and trigger.

Show answer

Answer: D The record ties the chosen interface to proof and future changes.

Retrieval practice

Recall check 3 of 3

Blueprint Bina says: answer from memory, then check your reasoning.

Q3A field switch bounces, uses a different logic level from the controller, and the line can surge. What must the interface review add?

AApprove wiring from a matching plug without level or idle-pull tests.

BCheck voltage and pulls; add level shift, debounce and surge guard.

CFix level mismatch in firmware after sampling the wrong pin voltage.

DRemove the pull path and allow the switch input to float on release.

Show answer

Answer: B The switch needs a safe electrical and timing boundary, not just a matching plug.

Print reference

Answers

Answer key.

D · A traceable power and interface decision proves the retained wake path, safe output defaults, signal limits, measured bursts, service behavior, and review conditions before the device depends on that hardware boundary.
D · The record ties the chosen interface to proof and future changes.
B · The switch needs a safe electrical and timing boundary, not just a matching plug.