Energy & Power · Study deck

Low-Power Design: Leakage and Body Bias

A transistor can leak even when it is off.

Battery Bruno is your guide for this deck.

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Battery Bruno, the module guide, in a scene from this chapter.

After studying this chapter

Learning objectives

You will be able to:

Test subthreshold slope and the leakage-speed trade with a concrete scenario and pass criteria.
Validate concrete nanowatt adc and input amplifier with a concrete scenario and pass criteria.
test subthreshold slope and the leakage-speed trade with a concrete scenario and pass criteria
validate concrete nanowatt adc and input amplifier with a concrete scenario and pass criteria

Major section

Subthreshold Slope and the Leakage-Speed Trade

A MOSFET does not become an ideal open switch when $V_{GS}$ crosses below threshold.

where $U_T=kT/q$ is thermal voltage and $n\ge1$ is the subthreshold slope factor.
Taking a base-10 logarithm gives.
The subthreshold swing—the gate-voltage change needed for one decade of drain-current change—is therefore.

Log drain current versus gate voltage for a low-V~T~ and a high-V~T~ device: parallel subthreshold slopes, off-currents decades apart, on-currents close together.

Major section

Subthreshold Slope and the Leakage-Speed Trade (continued)

At 300 K, $kT/q\approx25.85$ mV, so the ideal $n=1$ limit is $S\approx59.6$ mV/decade.

The often quoted “60 mV per decade” is thus not simply $kT/q$; it includes $\ln10$, and practical devices have $n>1$.
Higher temperature makes the slope worse.
Lower drive current increases delay.

Major section

FD-SOI Forward and Reverse Body Bias

The body is depleted, and the isolated back gate can electrostatically shift threshold with less junction leakage than a conventional bulk body connection.

Flipped-well layouts can make wider back-bias choices available for low-threshold devices, while regular-threshold arrangements use different well and nominal-bias connections.

FD-SOI body bias: the well under the buried oxide acts as a back gate; forward bias lowers the threshold for speed, reverse bias raises it for decades less leakage.

Major section

FD-SOI Forward and Reverse Body Bias (continued)

The exact safe rails—sometimes spanning several volts in a characterized FD-SOI process—are process rules, not portable firmware constants.

for NMOS under the sign convention above, where $\eta$ is the process-dependent body factor.
Substituting the shifted $V_T$ into the weak-inversion equation shows why a modest reverse bias can reduce $I_{OFF}$ exponentially.
That asymmetry is what an adaptive bias schedule exploits.

Major section

FD-SOI Forward and Reverse Body Bias (continued)

Substituting it into an on-current model such as $I_{ON}\propto(V_{GS}-V_T)^\alpha$ shows the simultaneous loss of drive.

An adaptive policy can therefore apply forward bias for a deadline-bound active burst and reverse bias during a long retained sleep.
It must budget bias-generator current, rail-settling time, reliability limits, temperature, and the energy of changing modes.
Firmware should select only documented operating points and wait for the silicon's ready indication; transistor cross-sections and well voltages belong to the chip's process documentation.

Major section

Low-Frequency Front-End Noise

A sample-and-hold and ADC then create discrete-time codes for digital processing.

Below that line the converter contributes kT/C and quantization terms of its own, and the closing card states the rule the whole budget rests on: everything added upstream is baked into the samples.

Anatomy of an analog-digital interface: sensor, low-noise amplifier, anti-alias filter, sample-and-hold, SAR ADC with reference, and the digital word — each stage annotated with its noise contribution and energy cost.

Major section

Low-Frequency Front-End Noise (continued)

The corner $f_c$ is where $K_f/f_c^\alpha=S_{white}$.

Below $f_c$, integrating flicker noise over $f_L$ to $f_H$ for $\alpha=1$ gives.
If the signal spectrum sits below $f_c$, the amplifier's offset, drift, and flicker noise can swamp it before the ADC sees a useful separation.
The review must therefore compare input-referred signal range, offset after calibration, integrated noise across the actual bandwidth, and ADC LSB size at the amplifier output.

Major section

Chopper Amplifier Signal Path

Chopper stabilization separates a low-frequency input from the amplifier's own low-frequency error by multiplying twice with a square wave $m(t)\in\{-1,+1\}$.

The amplifier processes that modulated signal.
Its offset and internal $1/f$ noise are added after the first mixer and therefore remain near baseband at this point.
Chopping is not magic.

The chopper path — mixer, amplifier, mixer, low-pass filter — and the spectrum at three points: the signal rides out to odd harmonics of f_chop and back, while offset and 1/f noise make only the outward trip.

Major section

Chopper Amplifier Signal Path (continued)

The amplifier offset and low-frequency noise are multiplied only once, so they move to $f_{chop}$ and its odd harmonics.

A low-pass filter passes the recovered sensor band and rejects the translated error and switching artifacts.
An ideal 50% square wave has odd-harmonic coefficients proportional to $1/(2k+1)$, so the first modulation produces replicas around $f_{chop},3f_{chop},5f_{chop},\ldots$.
The small gray chop artifacts at even harmonics are the residue real switches add.

Major section

Concrete Nanowatt ADC and Input Amplifier

A 1 ksample/s converter has a 1 ms sample period.

If off-state power were negligible, the equivalent active power during the 5 $\mu$s window would be $1\ \text{nW}/0.005=200$ nW.
The paired input amplifier provides a separate lesson.
The reported input-referred noise of 26 $\mu$V rms becomes about.

A nanowatt front end as two contracts: a SAR ADC active for 5 µs of every 1 ms sample period, and an AC-coupled 32 dB amplifier whose slow DC servo returns the output baseline to the input.

Major section

Concrete Nanowatt ADC and Input Amplifier (continued)

A real ledger must keep clock generation, reference settling, leakage, tracking, and output logic in the appropriate window rather than attributing everything to the comparator search.

AC coupling blocks sensor and electrode DC offsets from consuming output range, while a slow DC-servo loop feeds back the residual output baseline so the signal path remains centered.
A stated 370 Hz bandwidth then bounds the upper useful signal content and informs anti-alias filtering before 1 ksample/s conversion.
The result is compelling precisely because it is a complete front-end timing and noise contract, not because “nanowatt” appears on one block.

Deck summary

Key takeaways

A MOSFET does not become an ideal open switch when $V_{GS}$ crosses below threshold.

At 300 K, $kT/q\approx25.85$ mV, so the ideal $n=1$ limit is $S\approx59.6$ mV/decade.
The body is depleted, and the isolated back gate can electrostatically shift threshold with less junction leakage than a conventional bulk body connection.
The exact safe rails—sometimes spanning several volts in a characterized FD-SOI process—are process rules, not portable firmware constants.
Substituting it into an on-current model such as $I_{ON}\propto(V_{GS}-V_T)^\alpha$ shows the simultaneous loss of drive.

Retrieval practice

Recall check

Battery Bruno says: answer from memory, then check your reasoning.

Q1A chip designer raises transistor threshold to reduce standby leakage. Which competing effect should be expected?

AZero off-current once the gate is below threshold

BA temperature-independent standby behavior

CLess on-state drive and increased delay

DGreater speed with the same control voltage

Show answer

Answer: C The chapter links reduced leakage to lower overdrive and slower switching.

Q2An FD-SOI design applies reverse body bias to save standby energy. What trade-off does the table predict?

ASafe bias rails copied unchanged across processes

BHigher threshold magnitude and lower drive speed

CLower threshold magnitude with reduced leakage

DHigher speed without an off-current change

Show answer

Answer: B Reverse bias reduces off-current while reducing on-current and speed.

Print reference

Answers

Answer key.

C · The chapter links reduced leakage to lower overdrive and slower switching.
B · Reverse bias reduces off-current while reducing on-current and speed.