Electronics & Circuits · Study deck
Serial Bus Interface Contracts
Picture a light sensor and a display sharing a small controller board.
Voltage Vera is your guide for this deck.
After studying this chapter
Learning objectives
You will be able to:
- Select I2C, SPI, or UART from pin count, speed, addressing, and wiring constraints.
- Explain why I2C uses open-drain outputs and pull-up resistors on shared wires.
- Calculate UART byte timing from baud rate and frame format.
- Diagnose I2C rise-time limits from bus capacitance, pull-up strength, and sink-current limits.
Major section
Start Simple
A microcontroller means the small computer on the board.
- GPIO means general purpose input and output pins.
- Inter-integrated circuit (I2C) means a short shared wired link between chips.
- Serial Peripheral Interface (SPI) means a clocked wired link with separate data paths.
- Universal asynchronous receiver-transmitter (UART) means a serial link that agrees on timing without a shared clock.
Major section
Overview: How the Electronics Reach the Microcontroller
Those differences lead directly into the chapter's contract: record baud and frame for UART, pull-ups and addresses for I2C, or clock mode and chip-select timing for SPI.
- The schematic promises which pins exist, whether a line is shared, where pull-up resistors live, and how much capacitance the trace and cable add.
Major section
Overview: How the Electronics Reach the Microcontroller (continued)
The firmware promises the bus speed, address, chip-select timing, SPI mode, UART frame, retry behavior, and timeout policy.
- The peripheral promises the electrical levels it can tolerate and the protocol timing it will obey.
- SPI gives deterministic high-speed transfers to displays, radios, flash, or ADCs, but each added peripheral consumes routing and chip-select discipline.
- SPI Four wires ( SCLK, MOSI, MISO, CS ), push-pull, full-duplex, fast, one chip-select per device.
Major section
Practitioner: The Numbers That Define Each Bus
Worked example — UART framing at 9600 8N1. "8N1" means 8 data bits, no parity, 1 stop bit, wrapped by 1 start bit — 10 bit-times per byte.
- An I2C scan proves addresses acknowledge, but it does not prove the rise time is legal under worst-case temperature and cable length.
Major section
Practitioner: The Numbers That Define Each Bus (continued)
A UART terminal prompt proves baud alignment, but it does not prove binary framing, flow control, or recovery after a reset.
- At 9600 baud each bit lasts 1 / 9600 = 104 µs, so one byte takes about 10 × 104 µs = 1.04 ms, giving roughly 960 bytes/s.
- I2C's 2^7 address space is why you can hang a dozen sensors on two wires, while SPI trades that for speed by giving every device its own chip-select line.
- At: P — STOP condition, SDA rises while SCL is high and releases the bus.
Major section
Practitioner: The Numbers That Define Each Bus (continued)
The table distinguishes I2C by wire count and addressing, but a logic trace is needed to recognize its framing.
- If two sensors have the same fixed address, the design needs a different variant, a bus switch, a second controller bus, or SPI/UART instead of hoping firmware can separate them.
- For SPI, count one chip-select per peripheral plus any reset or data-ready lines, then verify the controller and peripheral sample on the same CPOL/CPHA edge before board bring-up.
- The next eight clocks carry: D7 through: D0, followed by a second: ACK, before the: STOP condition releases the bus.
Major section
Under the Hood: Each Bus's Electrical Catch
The buses inherit both the strengths and the limits of their output style.
- I2C is open-drain, so every rising edge is driven only by the passive pull-up charging the bus capacitance (an RC curve).
- The deeper reason these failures look different is that the receiver decides truth at a specific voltage and instant.
- On I2C, a controller samples SDA while SCL is HIGH, so a slow SDA rise can be read as LOW even though the firmware "released" the line.
Deck summary
Key takeaways
A microcontroller means the small computer on the board.
- Those differences lead directly into the chapter's contract: record baud and frame for UART, pull-ups and addresses for I2C, or clock mode and chip-select timing for SPI.
- The firmware promises the bus speed, address, chip-select timing, SPI mode, UART frame, retry behavior, and timeout policy.
- Worked example — UART framing at 9600 8N1. "8N1" means 8 data bits, no parity, 1 stop bit, wrapped by 1 start bit — 10 bit-times per byte.
- A UART terminal prompt proves baud alignment, but it does not prove binary framing, flow control, or recovery after a reset.
Retrieval practice
Recall check 1 of 3
Voltage Vera says: answer from memory, then check your reasoning.
Q1Which serial bus uses just two open-drain wires with pull-up resistors and selects devices by a 7-bit address?
Show answer
Answer: A I2C's two open-drain wires with pull-ups let many devices share the bus, each responding to its 7-bit address.
Retrieval practice
Recall check 2 of 3
Voltage Vera says: answer from memory, then check your reasoning.
Q2A design needs several addressable sensors but has very few spare pins and only moderate speed requirements. Which bus fits best, and why?
Show answer
Answer: D I2C's two shared, addressed wires suit a pin-constrained board with several moderate-speed devices at typical 100-400 kHz speeds; SPI would need a chip-select pin per device.
Retrieval practice
Recall check 3 of 3
Voltage Vera says: answer from memory, then check your reasoning.
Q3An I2C bus with many devices on long wires will not run reliably at 400 kHz. Given that I2C is open-drain, what is the cause and the lever?
Show answer
Answer: A Open-drain HIGHs are passive RC edges, so bus capacitance caps speed.
Print reference
Answers
Answer key.
- A · I2C's two open-drain wires with pull-ups let many devices share the bus, each responding to its 7-bit address.
- D · I2C's two shared, addressed wires suit a pin-constrained board with several moderate-speed devices at typical 100-400 kHz speeds; SPI would need a chip-select pin per device.
- A · Open-drain HIGHs are passive RC edges, so bus capacitance caps speed.