Electronics & Circuits · Study deck

Serial Bus Interface Contracts

Picture a light sensor and a display sharing a small controller board.

Voltage Vera is your guide for this deck.

serialinterface

Voltage Vera, the module guide, in a scene from this chapter.

After studying this chapter

Learning objectives

You will be able to:

Select I2C, SPI, or UART from pin count, speed, addressing, and wiring constraints.
Explain why I2C uses open-drain outputs and pull-up resistors on shared wires.
Calculate UART byte timing from baud rate and frame format.
Diagnose I2C rise-time limits from bus capacitance, pull-up strength, and sink-current limits.

Major section

Start Simple

A microcontroller means the small computer on the board.

GPIO means general purpose input and output pins.
Inter-integrated circuit (I2C) means a short shared wired link between chips.
Serial Peripheral Interface (SPI) means a clocked wired link with separate data paths.
Universal asynchronous receiver-transmitter (UART) means a serial link that agrees on timing without a shared clock.

Major section

Overview: How the Electronics Reach the Microcontroller

Those differences lead directly into the chapter's contract: record baud and frame for UART, pull-ups and addresses for I2C, or clock mode and chip-select timing for SPI.

The schematic promises which pins exist, whether a line is shared, where pull-up resistors live, and how much capacitance the trace and cable add.

UART, I2C, and SPI compared by their physical connection topology.

Major section

Overview: How the Electronics Reach the Microcontroller (continued)

The firmware promises the bus speed, address, chip-select timing, SPI mode, UART frame, retry behavior, and timeout policy.

The peripheral promises the electrical levels it can tolerate and the protocol timing it will obey.
SPI gives deterministic high-speed transfers to displays, radios, flash, or ADCs, but each added peripheral consumes routing and chip-select discipline.
SPIFour wires ( SCLK, MOSI, MISO, CS ), push-pull, full-duplex, fast, one chip-select per device.

Major section

Practitioner: The Numbers That Define Each Bus

Worked example — UART framing at 9600 8N1. "8N1" means 8 data bits, no parity, 1 stop bit, wrapped by 1 start bit — 10 bit-times per byte.

An I2C scan proves addresses acknowledge, but it does not prove the rise time is legal under worst-case temperature and cable length.

I2C START and STOP conditions distinguished from address and data transitions.

Major section

Practitioner: The Numbers That Define Each Bus (continued)

A UART terminal prompt proves baud alignment, but it does not prove binary framing, flow control, or recovery after a reset.

At 9600 baud each bit lasts 1 / 9600 = 104 µs, so one byte takes about 10 × 104 µs = 1.04 ms, giving roughly 960 bytes/s.
I2C's 2^7 address space is why you can hang a dozen sensors on two wires, while SPI trades that for speed by giving every device its own chip-select line.
At: P — STOP condition, SDA rises while SCL is high and releases the bus.

Major section

Practitioner: The Numbers That Define Each Bus (continued)

A high value in either ACK slot is a NACK, so the trace reveals whether the addressed device accepted the request and the data phase—not merely whether seven address bits were present.

If two sensors have the same fixed address, the design needs a different variant, a bus switch, a second controller bus, or SPI/UART instead of hoping firmware can separate them.
For SPI, count one chip-select per peripheral plus any reset or data-ready lines, then verify the controller and peripheral sample on the same CPOL/CPHA edge before board bring-up.
The next eight clocks carry: D7 through: D0, followed by a second: ACK, before the: STOP condition releases the bus.

Major section

Under the Hood: Each Bus's Electrical Catch

The buses inherit both the strengths and the limits of their output style.

I2C is open-drain, so every rising edge is driven only by the passive pull-up charging the bus capacitance (an RC curve).
The deeper reason these failures look different is that the receiver decides truth at a specific voltage and instant.
On I2C, a controller samples SDA while SCL is HIGH, so a slow SDA rise can be read as LOW even though the firmware "released" the line.

Deck summary

Key takeaways

A microcontroller means the small computer on the board.

Those differences lead directly into the chapter's contract: record baud and frame for UART, pull-ups and addresses for I2C, or clock mode and chip-select timing for SPI.
The firmware promises the bus speed, address, chip-select timing, SPI mode, UART frame, retry behavior, and timeout policy.
Worked example — UART framing at 9600 8N1. "8N1" means 8 data bits, no parity, 1 stop bit, wrapped by 1 start bit — 10 bit-times per byte.
A UART terminal prompt proves baud alignment, but it does not prove binary framing, flow control, or recovery after a reset.

Retrieval practice

Recall check 1 of 5

Voltage Vera says: answer from memory, then check your reasoning.

Q1Which serial bus uses just two open-drain wires with pull-up resistors and selects devices by a 7-bit address?

AI2C, with SDA/SCL open-drain pull-ups and 7-bit device addresses

BSPI, with two open-drain wires and seven-bit device addresses

CUART, with device addresses on a shared open-drain wire pair

DAll three buses, with identical wiring and address selection

Show answer

Answer: A I2C's two open-drain wires with pull-ups let many devices share the bus, each responding to its 7-bit address.

Retrieval practice

Recall check 2 of 5

Voltage Vera says: answer from memory, then check your reasoning.

Q2A design needs several addressable sensors but has very few spare pins and only moderate speed requirements. Which bus fits best, and why?

ASPI because chip-select pins supposedly cost less than I2C's two wires

BUART because its point-to-point link supposedly addresses many sensors

CAny bus because sensor address and pin counts supposedly match

DI2C because many addressed sensors share two moderate-speed wires

Show answer

Answer: D I2C's two shared, addressed wires suit a pin-constrained board with several moderate-speed devices at typical 100-400 kHz speeds; SPI would need a chip-select pin per device.

Retrieval practice

Recall check 3 of 5

Voltage Vera says: answer from memory, then check your reasoning.

Q3A UART frame has one start bit, eight data bits, and one stop bit at a baud rate of nine thousand six hundred bits per second. About how long is one frame?

AAn indeterminate frame duration without a shared clock signal

BA duration near 1 ms for ten bits at 9,600 bits per second

CA duration near 0.1 ms by counting the whole frame as one bit

DUse a duration near 10 ms because serial framing stretches the transfer at the stated bit rate.

Show answer

Answer: B Ten bits divided by the bit rate gives about one millisecond.

Retrieval practice

Recall check 4 of 5

Voltage Vera says: answer from memory, then check your reasoning.

Q4Two SPI peripherals share the clock and data lines. What must the controller set for each transfer?

ASelect one device and set its required SPI clock polarity and phase.

BSelect both SPI devices at once on the shared return-data wire.

CSelect a device using an I2C address rather than chip select.

DSelect no clock mode because connected wires supposedly suffice.

Show answer

Answer: A Chip-select and mode must match the active device.

Retrieval practice

Recall check 5 of 5

Voltage Vera says: answer from memory, then check your reasoning.

Q5An I2C bus with many devices on long wires will not run reliably at 400 kHz. Given that I2C is open-drain, what electrical cause should the review investigate first?

ATotal bus capacitance slows passive RC pull-up edges on SDA and SCL.

BMore I2C devices supposedly speed open-drain edges, so blame software.

CMore frame data bits supposedly fix the slow electrical rising edge.

DPull-up removal supposedly makes I2C fast push-pull signaling.

Show answer

Answer: A Open-drain HIGHs are passive RC edges, so bus capacitance caps speed.

Print reference

Answers 1 of 2

Answer key.

A · I2C's two open-drain wires with pull-ups let many devices share the bus, each responding to its 7-bit address.
D · I2C's two shared, addressed wires suit a pin-constrained board with several moderate-speed devices at typical 100-400 kHz speeds; SPI would need a chip-select pin per device.
B · Ten bits divided by the bit rate gives about one millisecond.
A · Chip-select and mode must match the active device.

Print reference

Answers 2 of 2

Answer key.

A · Open-drain HIGHs are passive RC edges, so bus capacitance caps speed.