Electronics & Circuits · Study deck

ADC Fundamentals: Architectures and Interfaces

Resolution describes the converter's code steps, but a bit count alone does not choose the converter.

Voltage Vera is your guide for this deck.

analogdigital

Voltage Vera, the module guide, in a scene from this chapter.

After studying this chapter

Learning objectives

You will be able to:

Explain: For an ideal converter that rounds to the nearest level, its magnitude is bounded by roughly half a step: $V_{ref}/2^{n+1}$ for a unipolar span from zero to $V_{ref}$ .
Explain: The big picture: A successive approximation register (SAR) ADC performs a 12-step binary search to determine which of 4,096 discrete voltage levels most closely matches the analog sensor input.
Explain: Chopper-stabilised front ends, modulation techniques, careful component choice, and a bandwidth appropriate to the signal are possible controls; the correct choice depends on whether the wanted measurement includes DC.

Major section

ADC Architectures

Once the voltage step is clear, the next question is how the converter finds that code.

The architecture determines whether the design prioritizes microsecond conversion, high resolution, low current, or simple integration.
The sample-and-hold keeps the unknown input steady.
The logic keeps or clears one bit and repeats with a finer proposal.

SAR ADCs dominate IoT applications due to their balance of speed, resolution, and power efficiency.

Major section

ADC Architectures (continued)

SAR logic proposes a code, the internal DAC turns that proposal into a comparison voltage, and the comparator reports whether the proposal is above or below the held input.

That feedback loop is the physical meaning of the “binary search” described next.
SAR is a balanced choice, not a universal winner.
A flash ADC makes many comparisons in parallel, trading circuit area and power for very low conversion latency.

ADC Fundamentals Complete -> Next: Nyquist Sampling Theory

Major section

ADC Architectures (continued)

A sigma-delta ADC uses oversampling, feedback, and digital filtering to favour fine low-bandwidth measurements over immediate results.

It often fits a built-in ADC when no one extreme rules the choice.
Its filter delay may then be worth the lower band noise and finer useful detail.
The inner conversion method follows two system facts: how fast the signal can change, and how small a change the result must show with trust.

Flash, Pipeline, SAR, and Sigma-Delta ADC architectures positioned by relative speed and resolution, with SAR as the balanced default most IoT microcontrollers use.

Major section

Analog-Digital Interface Challenges

Architecture is only part of measurement quality.

The front end still has to protect the ADC from noise, source impedance, reference drift, and out-of-band signal content.
Flicker noise matters near DC, thermal noise grows with resistance and bandwidth, rail disturbance can couple from switching loads, and sampling-time uncertainty corrupts when the input is observed.

ADC uncertainty enters through the signal path, rails, components, sampling time, and unavoidable code quantization, so remedies must target the mechanism.

Major section

Analog-Digital Interface Challenges (continued)

A higher-resolution converter makes that ideal step smaller.

Quantization remains even after those mechanisms are controlled.
The chapter's diagnostic order is therefore to locate uncertainty, control its mechanism, and only then decide whether code resolution is limiting.
Thermal Noise (Johnson-Nyquist Noise): Thermal noise is random voltage noise associated with resistance and temperature.

A round light-dependent resistor (LDR) with an orange zigzag cadmium-sulfide track and two leads

Major section

Analog-Digital Interface Challenges (continued)

Quantization Noise (Inherent ADC Limitation): Quantization error is the difference between the input and the representative level selected for its code.

For an ideal converter that rounds to the nearest level, its magnitude is bounded by roughly half a step: $V_{ref}/2^{n+1}$ for a unipolar span from zero to $V_{ref}$ .
Oversampling and averaging can reveal finer information when suitable noise moves the signal across code boundaries, but they do not correct reference error, clipping, or systematic nonlinearity.
Simply collecting more readings may not help as much as it would for independent white noise because successive errors can be correlated.

Major section

Analog-Digital Interface Challenges (continued)

Because the other errors enter earlier, more bits cannot cure them.

Chopper-stabilised front ends, modulation techniques, careful component choice, and a bandwidth appropriate to the signal are possible controls; the correct choice depends on whether the wanted measurement includes DC.
Its RMS value over bandwidth $Δf$ is described by $V_{rms}=\sqrt{4kTR\Delta f}$ .
Averaging can reduce the contribution when samples are sufficiently independent, but it trades response time for lower random uncertainty.

Major section

Typical Microcontroller ADCs

LSB = Least Significant Bit (smallest measurable change).

Everything below that boundary operates on the resulting code: processing may calibrate or convert units, formatting gives the reading a data representation, and packet and network stages move it elsewhere.

From physical measurement through signal conditioning and ADC conversion to the downstream digital stages that turn a raw reading into usable system data.

Major section

Real-World IoT ADC Applications

Each connection corresponds to a question the application table must answer.

The digital side prompts questions about how quickly results are needed and how the processor will read them.
The opening light-sensor example is a useful concrete case.

A 10–12-bit built-in ADC example converts an LDR voltage-divider sensor input into a digital code using a defined reference voltage.

Major section

SAR ADC Sensor Conversion

The big picture: A successive approximation register (SAR) ADC performs a 12-step binary search to determine which of 4,096 discrete voltage levels most closely matches the analog sensor input.

The sample-and-hold first freezes the sensor's 2.0 V input, giving the comparator a stable target.
The next proposal adds half of the remaining range, producing 2.475 V; that proposal is too high, so the next bit is cleared.
By the time the least-significant bit has been tested, the register itself is the output code.
Because the held input is higher, the most-significant bit remains set.

Major section

Summary

At every branch, carry forward the input range, reference quality, and noise evidence established earlier.

Bandwidth constrains how quickly the converter and front end must respond.
The destination boxes are starting classes for investigation; a real selection still requires data-sheet limits and measurements.

Start with signal bandwidth, sensor accuracy, and power budget before deciding whether a simple 8-bit, default 10-12-bit, or precision 16-bit ADC is justified.

Deck summary

Key takeaways

Once the voltage step is clear, the next question is how the converter finds that code.

SAR logic proposes a code, the internal DAC turns that proposal into a comparison voltage, and the comparator reports whether the proposal is above or below the held input.
A sigma-delta ADC uses oversampling, feedback, and digital filtering to favour fine low-bandwidth measurements over immediate results.
Architecture is only part of measurement quality.
A higher-resolution converter makes that ideal step smaller.

Retrieval practice

Recall check 1 of 5

Voltage Vera says: answer from memory, then check your reasoning.

Q1You're designing a battery-powered IoT scale that needs to measure 0.1 gram changes across a 100 kg range at a few readings per second. Which ADC architecture is most appropriate?

AFlash ADC - for fastest response time

BSAR ADC - built into most microcontrollers

CPipeline ADC - for video-rate sampling

DSigma-Delta ADC - highest resolution

Show answer

Answer: D Precision weighing requires high resolution (16-24 bit) to detect small weight changes.

Retrieval practice

Recall check 2 of 5

Voltage Vera says: answer from memory, then check your reasoning.

Q2Your temperature sensor readings show random, zero-mean fluctuations of +/-5 counts even when the temperature is stable. What is the most effective first step to reduce this noise?

AUpgrade to a 16-bit ADC for higher resolution

BAverage 16-64 samples to reduce random noise

CIncrease the sampling rate to capture more data

DUse a faster microcontroller for quicker processing

Show answer

Answer: B Averaging multiple samples is the most cost-effective way to reduce random noise.

Retrieval practice

Recall check 3 of 5

Voltage Vera says: answer from memory, then check your reasoning.

Q3Which ADC resolution provides the smallest quantization error for a 5V reference?

A16-bit (0.076 mV/step)

B8-bit (19.5 mV/step)

C10-bit (4.88 mV/step)

D12-bit (1.22 mV/step)

Show answer

Answer: A Higher resolution (more bits) = smaller step size = lower quantization error.

Retrieval practice

Recall check 4 of 5

Voltage Vera says: answer from memory, then check your reasoning.

Q4You're measuring a 2.5V signal with an ESP32's 12-bit ADC (3.3V reference). The sensor's absolute accuracy is +/-2% of its 2.5V reading. Which stated limit dominates the absolute measurement error?

ASensor accuracy dominates the error budget

BThe 12-bit resolution (0.8mV steps) is the limiting factor

CThe ESP32's ADC is too noisy for precision measurements

DYou need a 16-bit ADC for reliable measurements

Show answer

Answer: A see answers page

Q5What source voltage must enter an ADC within its allowed input range?

AAnalog input

BAnti-alias filter

CSample-and-hold

DReference voltage

Show answer

Answer: A The source voltage must enter the converter within its allowed range.

Retrieval practice

Recall check 5 of 5

Voltage Vera says: answer from memory, then check your reasoning.

Q6You're designing an environmental monitoring station with an analog humidity sensor spanning 0-3.3V. Its output error is +/-66mV (2% of that span), and readings update every 10 seconds. What ADC approach is most cost-effective?

AAdd an external 24-bit ADS1256 for maximum precision

BUse the ESP32's built-in 12-bit ADC with software averaging

CUse a fast 8-bit flash ADC for real-time response

DImplement a 16-bit pipeline ADC for balanced performance

Show answer

Answer: B see answers page

Print reference

Answers 1 of 3

Answer key.

D · Precision weighing requires high resolution (16-24 bit) to detect small weight changes.
B · Averaging multiple samples is the most cost-effective way to reduce random noise.
A · Higher resolution (more bits) = smaller step size = lower quantization error.

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Answers 2 of 3

Answer key.

A · The sensor's +/-2% accuracy = +/-50mV error, while the ADC's 0.8mV code spacing is about 62 times finer. Adding a higher-resolution ADC alone won't improve absolute accuracy when the sensor itself has +/-50mV uncertainty. This is why matching ADC resolution to sensor accuracy prevents wasted cost on unnecessary precision.
A · The source voltage must enter the converter within its allowed range.

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Answers 3 of 3

Answer key.

B · s 12-bit resolution (0.8mV).