Electronics & Circuits · Study deck

ADC Architecture and Resolution

Picture a fast motor-current pulse and a slow strain reading.

Voltage Vera is your guide for this deck.

analogdigitalresolution

Voltage Vera, the module guide, in a scene from this chapter.

After studying this chapter

Learning objectives

You will be able to:

Choose SAR or sigma-delta ADCs based on speed, resolution, latency, and IoT signal bandwidth.
Calculate least significant bit size and separate converter resolution from usable measurement accuracy.
Check SAR source impedance, sample-capacitor settling, and acquisition-time constraints before trusting readings.
Use oversampling only when throughput and dither/noise conditions can support extra effective bits.

Major section

Start Simple

Two converters can advertise the same number of bits yet miss different parts of those signals.

An analog-to-digital converter is a circuit that turns a measured voltage into a number; ADC is its short name.
Bandwidth means the range of signal changes the measurement path must carry.
Latency means the time from an input change to the result that matters.
This runway does not prove that one converter design is best for every sensor.

Major section

Phoebe's Field Notes: Where +9 dB and +15 dB Per Octave Come From

The mathematical gist: An order- $L$ noise shaper makes in-band quantisation-noise power fall as $1/OSR^{2L+1}$ .

At first order and OSR 64, the idealised gain is 54.2 dB, or 9.00 bits.

Major section

Practitioner: The Two Constraints That Bite in Real Circuits

The signal first charges the sample-and-hold capacitor.

The capacitor must settle before that search starts.
If it does not, each later choice can be exact yet based on the wrong held voltage.

SAR ADC architecture showing analog input sampled by a sample-and-hold stage, compared against DAC feedback controlled by the SAR register, and emitted as a digital output code.

Major section

Choose an ADC for a Millivolt Bridge

For this ADC architecture, a pressure bridge changes by only a few millivolts while a nearby motor throws fast noise onto its cable.

At the converter resolution boundary, a code is trustworthy only after the input node has settled far enough.
At the converter resolution boundary, oversampling does not create information from a fixed error.

Major section

Choose an ADC for a Millivolt Bridge (continued)

A stable 3 mV offset remains 3 mV after any number of averages.

In the millivolt architecture, for a 0–3.3 V, 12-bit ADC, one ideal step is $3.3/4096=0.000806\ \text{V}$ , or 0.806 mV.
For this ADC architecture, a 6 mV bridge change spans only $6/0.806=7.44$ ideal codes before noise and offset.
The bridge also sets a rate limit.

Major section

Choose an ADC for a Millivolt Bridge (continued)

Adding a gain of 100 would turn 6 mV into 0.600 V, but the amplifier’s offset, range, bandwidth, and saturation then enter the ADC architecture contract.

In the millivolt architecture, with suitable independent noise, averaging four samples cuts the random part by √4 and can add about one effective bit.
A sigma-delta ADC may trade bandwidth for strong low-frequency resolution, while a SAR ADC may suit a faster multiplexed path; the pressure signal’s job decides which trade is useful.
The final ADC choice should state its usable input span, settled rate, measured noise, and allowed source resistance.

Major section

Choose an ADC for a Millivolt Bridge (continued)

If useful pressure changes end at 20 Hz, the ADC must sample above 40 samples/s before transition space is allowed.

A practical rate needs room for the analogue filter to fall before Nyquist.
At 200 samples/s, Nyquist is 100 Hz, leaving an 80 Hz transition band above the 20 Hz signal.
The chosen ADC architecture must then deliver settled codes at that rate, not merely advertise a much faster serial clock.

Major section

Release Checklist

LSB size is calculated from Vref / 2^N and compared with sensor accuracy, reference noise, and analog-front-end noise.

SAR acquisition time is long enough for the source impedance and sample capacitor to settle within the target error band.
Any high-impedance divider or sensor output is buffered, slowed, or sampled with an acquisition time supported by the data sheet.
Sigma-delta latency, decimation-filter delay, and update rate are acceptable for the control loop or telemetry interval.

Deck summary

Key takeaways

Two converters can advertise the same number of bits yet miss different parts of those signals.

The mathematical gist: An order- $L$ noise shaper makes in-band quantisation-noise power fall as $1/OSR^{2L+1}$ .
The signal first charges the sample-and-hold capacitor.
For this ADC architecture, a pressure bridge changes by only a few millivolts while a nearby motor throws fast noise onto its cable.
A stable 3 mV offset remains 3 mV after any number of averages.

Retrieval practice

Recall check 1 of 6

Voltage Vera says: answer from memory, then check your reasoning.

Q1An ADC has a 3.2 V reference and a 10-bit output. Which claim follows?

AA 3.2 mV code step that supposedly proves the sensor is accurate

BA 3.125 mV ideal step with accuracy still requiring measurement

CA 0.3125 mV code step that supposedly makes analog noise irrelevant

DA 3.125 V code step that supposedly prevents small-change measurement

Show answer

Answer: B Code size follows the reference and bit count; noise and reference error can still dominate.

Retrieval practice

Recall check 2 of 6

Voltage Vera says: answer from memory, then check your reasoning.

Q2A load cell scale must resolve sub-gram weight changes but only needs a reading a few times per second. Which ADC architecture fits, and why?

AA fast SAR ADC so software averaging alone supplies the required sub-gram detail

BA flash ADC because parallel comparators supposedly yield the most resolution bits

CA lower-reference ADC because voltage per code alone supposedly ensures effective resolution

DA sigma-delta ADC for slow load-cell readings needing high effective resolution

Show answer

Answer: D Sigma-delta oversamples and noise-shapes to reach 16-24 bits, ideal for slow precision DC signals like load cells (the HX711 is a 24-bit sigma-delta made for exactly this).

Retrieval practice

Recall check 3 of 6

Voltage Vera says: answer from memory, then check your reasoning.

Q3A SAR sensor needs one more effective bit from averaging. Which plan could work?

ATake four identical codes without dither and claim an extra effective bit.

BTake one code and digitally filter it to recover unseen sub-code detail.

CTake four dithered readings and accept one quarter of the output rate.

DTake two identical readings while retaining the original output rate.

Show answer

Answer: C The extra bit costs samples, and code variation is needed.

Retrieval practice

Recall check 4 of 6

Voltage Vera says: answer from memory, then check your reasoning.

Q4You average 16 SAR readings of a very clean, essentially noise-free DC voltage to gain resolution, but every reading is the identical code and the average shows no extra resolution. What is the fix?

AIncrease Vref so each code spans more volts and supposedly improves resolution.

BAllow about 1 LSB of dither, then average adjacent-code readings for extra detail.

CSwitch the ADC to auto-acknowledge as if messaging settings controlled quantization.

DAverage fewer identical samples to claim more effective conversion bits.

Show answer

Answer: B Without dither, a clean DC input lands on a single code every time, so the average equals that code.

Retrieval practice

Recall check 5 of 6

Voltage Vera says: answer from memory, then check your reasoning.

Q5A sigma-delta converter makes a fast stream of coarse codes. What makes its slow output more precise?

ACopy every coarse code directly without rejecting out-of-band quantization noise.

BRaise bit count with a resistor divider before the sigma-delta conversion stage.

CShape noise upward, then decimate to filter that noise and lower the output rate.

DKeep high-frequency quantization noise in the slow output because decimation retains the original noise band.

Show answer

Answer: C Shaping and decimation trade update speed for useful in-band detail.

Retrieval practice

Recall check 6 of 6

Voltage Vera says: answer from memory, then check your reasoning.

Q6A first-order sigma-delta modulator's oversampling ratio is doubled (say 64x to 128x). Approximately how much does the ideal in-band SNR improve?

AAbout 3 dB per doubling, as with unshaped oversampling

BAbout 6 dB per doubling, like one extra quantizer bit

CAbout 0 dB because oversampling supposedly cannot affect SNR

DAbout 9 dB per doubling, or roughly 1.5 effective bits

Show answer

Answer: D First-order noise shaping yields about +9 dB (~1.5 bits) per doubling of the oversampling ratio, far more than the +3 dB of plain oversampling. First-order noise shaping gives about +9 dB per octave of oversampling ratio.

Print reference

Answers 1 of 2

Answer key.

B · Code size follows the reference and bit count; noise and reference error can still dominate.
D · Sigma-delta oversamples and noise-shapes to reach 16-24 bits, ideal for slow precision DC signals like load cells (the HX711 is a 24-bit sigma-delta made for exactly this).
C · The extra bit costs samples, and code variation is needed.
B · Without dither, a clean DC input lands on a single code every time, so the average equals that code.

Print reference

Answers 2 of 2

Answer key.

C · Shaping and decimation trade update speed for useful in-band detail.
D · First-order noise shaping yields about +9 dB (~1.5 bits) per doubling of the oversampling ratio, far more than the +3 dB of plain oversampling. First-order noise shaping gives about +9 dB per octave of oversampling ratio.