I2C/SPI Bus Visualizer

Compare I2C and SPI bus wiring, timing waveforms, addressing, chip-select, ACK, and clock-mode behavior.

A beginner-first interactive bus visualizer for learning when to choose I2C or SPI, how transactions are framed, and which signal-level details cause real hardware problems.

Animation I2C SPI Beginner First

I2C/SPI Bus Visualizer

Watch the same embedded-device conversation as bus wiring, protocol steps, and timing waveforms. The controls deliberately connect signal-level details to practical design choices.

I2Cselected protocol

STARTcurrent bus event

0.36 msestimated transfer time

Pull-up OKcurrent design check

Goal

Learn how I2C and SPI move bits, why their wiring differs, and which protocol fits a sensor, memory, or display task.

Try First

Step through I2C temperature read, then switch to SPI flash read and compare the wire count and timing.

Watch

The active bit marker, waveform rows, metric cards, and event log update together as the transaction advances.

Why It Matters

Many hardware bugs are not code bugs; they are pull-up, chip-select, clock-mode, or bus-loading mistakes.

1. Idle I2C lines idle HIGH through pull-ups. SPI clock idles according to CPOL and chip select is inactive.

2. Select I2C sends START and address. SPI pulls one CS line LOW.

3. Command The master sends register, command, or address bits while the clock defines sampling points.

4. Response I2C expects ACK/NACK after bytes. SPI usually has no bus-level ACK.

5. Data I2C data is half-duplex on SDA. SPI can shift MOSI and MISO at the same time.

6. Release I2C sends STOP or repeated START. SPI releases chip select HIGH.

2 sharedsignal wires

45 clocksframe clocks

400 kHzactive clock

Address and ACKcurrent lesson

Controls

Choose a bus and scenario, then adjust timing and loading. Use Step for inspection or Play for continuous motion.

Protocoltwo-wire shared bus

Scenarioregister read

Viewwaveform timing

Playbackmanual

Payload bytes 2 bytes

Data bytes after command or register selection.

I2C speed 400 kHz

Standard, Fast, and Fast Mode Plus timing bands.

I2C pull-up 4.7 kOhm

Weak pull-ups rise slowly; very strong pull-ups increase sink current.

Bus load 60 pF

Long wires and many devices add capacitance to I2C rise time.

SPI clock 8 MHz

Fast SPI is useful only if wiring and the peripheral support it.

SPI mode Mode 0

CPOL and CPHA must match on master and slave.

Waveform View

The waveform highlights the current bus event and the bit that the learner should inspect.

START

Reading: START begins an I2C transaction by pulling SDA LOW while SCL is HIGH.

Live Bus Decision

Use I2C when pin count and addressed shared devices matter more than raw throughput.

Bus eventSTART condition

Signal focusSDA while SCL HIGH

Frame roleselect transaction

Clock rulesample SDA when SCL HIGH

Design riskPull-up OK

Event Log

I2C Rule

I2C uses shared open-drain lines and pull-up resistors.

Every byte has a ninth ACK/NACK clock.

SPI Rule

SPI uses a separate chip-select path to choose the active peripheral.

Clock mode must match before data bits make sense.

Choice Rule

Choose the bus from wiring, speed, device count, and error-detection needs.

Fewer wires is not always better than simpler timing.

Beginner Ramp

• Serial bus: devices share a small number of signal wires and move bits in clocked order.
• Master: usually the microcontroller that starts the transaction and provides the clock.
• Peripheral: a sensor, memory, display, or converter responding to the master.
• Waveform: a time diagram showing whether each signal is LOW or HIGH.

I2C Quick Reference

• Signals: SCL clock and SDA bidirectional data.
• Lines are open-drain/open-collector style and normally need pull-up resistors.
• START: SDA falls while SCL is HIGH. STOP: SDA rises while SCL is HIGH.
• Data should be stable while SCL is HIGH, except during START and STOP.
• Each byte is followed by an ACK/NACK bit on the ninth clock.

SPI Quick Reference

• Signals: SCLK, MOSI, MISO, and one or more CS lines.
• SPI usually has no bus-level address or ACK; chip select chooses the peripheral.
• Full-duplex transfers shift MOSI and MISO at the same time.
• Mode 0: CPOL 0, CPHA 0. Mode 3: CPOL 1, CPHA 1. Both ends must agree.

Timing Formula Notes

• I2C frame clocks here use 9 clocks per byte: 8 data bits plus ACK/NACK.
• I2C rise time is estimated with 0.8473 * Rpullup * Cbus.
• Typical maximum I2C rise-time targets: 1000 ns at 100 kHz, 300 ns at 400 kHz, 120 ns at 1 MHz.
• SPI transfer time here is frame bits / SCLK; real devices may add command latency or wait states.

Choosing Safely

• Choose I2C for low pin count, many low-speed peripherals, and register-style sensors.
• Choose SPI for displays, flash, ADCs, or sensors that need high throughput or deterministic timing.
• Use logic-analyzer captures to confirm ACKs, chip select timing, and SPI mode before changing firmware.

Common Faults

• I2C: missing pull-ups, address mismatch, slow rise time, stuck SDA/SCL, or unsupported clock stretching.
• SPI: wrong CPOL/CPHA, wrong bit order, CS released too early, shared MISO contention, or clock too fast.
• Both: poor grounding, long jumpers, and weak level shifting can corrupt signals.

Practice 1

Select I2C temp, raise bus load to 400 pF, then compare weak and strong pull-ups. Explain what changes.

Practice 2

Select SPI flash and switch through modes 0-3. Identify the sample edge for each mode.

Practice 3

Select Design choice. Decide whether a small sensor board or fast display should use I2C or SPI and justify it.

Sensor-to-Network Data Pipeline

Follow sensor data after the bus transaction leaves the board.

Datasheet Navigator

Practice finding bus timing, electrical limits, and register maps.

IoT Troubleshooting Simulator

Diagnose hardware, firmware, and communication faults.