ADC Resolution Visualizer
Watch analog voltage become sampled ADC codes, then tune bits, reference voltage, and noise
ADC Resolution Visualizer
Watch a smooth sensor voltage move through sample-and-hold, quantization bins, and a digital code register. Then change the hardware settings to see what improves and what noise still hides.
Analog to Digital Conversion Animation
The moving cursor samples the analog wave. The ADC maps that sample into one code bin and emits the digital code shown below.
Fit for coarse monitoring
Learning Support
Beginner Model
Bits create bins. An 8-bit ADC has 256 bins, a 10-bit ADC has 1024 bins, and a 12-bit ADC has 4096 bins across the reference voltage.
Design Rule
Your ADC step should be smaller than the smallest useful sensor change. Extra bits do not help if sensor noise is larger than the step.
What to Notice
- More bits make the staircase finer.
- Lower reference voltage also makes each step smaller.
- Noise can make extra bits unusable.
Quick Reference
| Bits | Levels | 3.3 V Step | 5 V Step | Typical Fit |
|---|
Technical Notes
Code Width
This teaching model uses LSB = Vref / 2^N and code range 0 to 2^N - 1 for an ideal unipolar ADC.
Quantization Error
The displayed error band is the ideal +/-0.5 LSB model. Offset, gain, nonlinearity, reference tolerance, sampling error, and input noise are separate limits.
Noise-Limited Fit
Find Minimum now includes the selected noise-count estimate, so it does not recommend more bits while ignoring a noisy sensor path.