Math Bridge: I2C rise time

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Math BridgeDesign MethodologyStruggle-friendly runway

Why can a pull-up pass at 100 kHz and fail at 400 kHz?

Follow an open-drain I2C line from resistance and capacitance to the rise time a zero-capacitance simulator cannot reveal.

Blueprint Bina, the design guideBlueprint Bina guides
The one targetCalculate I2C rise time from R and C.
The chapter case80 pF bus; 10 kΩ pull-up; 100 and 400 kHz.
What it buys youA bench-transfer check the ideal model cannot pass for you.

A field team has a real problem to settle: Why can a pull-up pass at 100 kHz and fail at 400 kHz? They must decide what happens before they change pull-up on the device. Predict the direction first.

See the relationship first

The figure reads from left to right. The blue card is pull-up. The middle card uses this page's rule. The green card is rise time. Follow the arrows: set the input, use the rule, then read the result and its unit.

The audit later on checks more than one number. Here, the added model uses the baseline named below and holds every other chapter value fixed. That sentence bridges the fixtures, so the numbers do not change without a reason.

Pull-up changes rise time An input card leads through the page rule to the rise time result. SET INPUT ONE CONTROL USE RULE predict calculate check units READ RESULT
Follow the arrows. R and C multiply. Halving either one halves τ and therefore halves the 30%-to-70% rise time.

Derive the baseline in four moves

  1. 1

    Name the input. The chapter baseline for pull-up is 10.

  2. 2

    Name the rule. tr=0.847x10 kohmx80 pF=678 ns 678/300=2.26x the Fast-mode limit Rpu,max=300/(0.847x80)=4.43 kohm 678 ns is above 600 ns Fast high time but below 1,000 ns Standard rise limit

  3. 3

    Put in the chapter value. Set pull-up to 10. The page rule gives rise time as 678 ns.

  4. 4

    Read the result. Keep ns next to the value. Use it only within the limits on this page.

Predict, then change pull-up

Try Predict what happens to rise time. Move one control, calculate, then check your idea.

10
Chapter baseline
Rise time

Observe R and C multiply. Halving either one halves τ and therefore halves the 30%-to-70% rise time. Reset to 10 and compare rise time.

Explain Only pull-up moves here. The other chapter values stay fixed.

Check yourself

What should you do before you trust the result?
Answer: Predict its direction, use the shown rule, keep the units, and reset to the worked baseline.
What does this small model leave out?
Answer: Only pull-up moves. Field effects named in the page limits stay fixed.

Honesty note. This teaching model changes only pull-up. It replays the chapter baseline; it is not a field prediction.

1. A released line must charge

An I2C device pulls the line low but does not actively drive it high. When it lets go, the pull-up resistor supplies charge to every connected capacitance. More resistance or capacitance means a slower rise.

Blueprint Bina: An ideal digital edge hides the physical time budget.

2. Name the algebra moves

1

Form the time constantτ=RpuCbus.

2

Write the charge curveV(t)=VDD(1−e^(−t/τ)).

3

Solve two crossingsFind t at 0.3VDD and 0.7VDD.

4

Subtracttr=τ ln(0.7/0.3)=0.847RpuCbus.

5

Compare limitstr must stay below the mode's rise-time allowance.

3. Reproduce the breadboard case

tr=0.847×10 kΩ×80 pF=678 ns
678/300=2.26× the Fast-mode limit
Rpu,max=300/(0.847×80)=4.43 kΩ
678 ns is above 600 ns Fast high time but below 1,000 ns Standard rise limit

The same 10 kΩ part can appear fine at 100 kHz and fail after a speed change.

4. Try the pull-up

TryReduce the pull-up from 10 kΩ toward 2.2 kΩ while bus capacitance stays 80 pF.

Pull-up
Rise time
Fast limit ratio
Maximum pull-up
Fast high-time ratio
Standard limit ratio

ObserveRise time falls in direct proportion to resistance; the 4.43 kΩ boundary does not move unless capacitance or the mode limit changes.

ExplainR and C multiply. Halving either one halves τ and therefore halves the 30%-to-70% rise time.

Technical boundaries.

This first-order RC model is a transfer check, not a complete bus simulation.

Capacitance
Measure or bound every pin, trace, cable, connector, and probe
Thresholds
Actual input thresholds and clock timing vary by device and mode
Pull-up
Lower resistance increases sink current and must respect VOL and device limits

Confirm rise time, low level, setup, and hold on physical hardware.

5. Transfer the claim to the bench

Probe SDA and SCL at the farthest device with the final wiring. Test normal traffic, clock stretching, missing devices, and the intended supply range.

6. Record the interface state

Store pull-up, measured capacitance or rise time, bus rate, device count, wiring length, thresholds, firmware version, and oscilloscope setup.

7. Check yourself

Why does a virtual high edge prove too little?
Answer: An ideal node may omit the RC charging time entirely.
Why is 10 kΩ unsuitable here at 400 kHz?
Answer: Its 678 ns rise exceeds the 300 ns Fast-mode allowance.
Is 2.2 kΩ automatically safe?
Answer: No. Check sink current, low voltage, thresholds, and measured timing.
Honesty boundary.

The 80 pF and 10 kΩ case reproduces the chapter's catalog-typical breadboard example.

80 pF
Teaching estimate, not a measured final bus
0.847
30%-to-70% first-order RC factor
4.43 kΩ
Rise-time ceiling only, not the full electrical design

Correct, not complete: RC arithmetic does not qualify an I2C interface.

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