Math Bridge: How can a clean sample still arrive at the wrong time?

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How can a clean sample still arrive at the wrong time?

Keep signal capture, voltage rounding, and timestamp drift in three separate columns.

Data Dora, the guideData Dora guides
The one targetExplain why 50 ppm becomes 18 sample intervals in one hour.
The chapter case100 Hz summaries, 50 ppm drift, 12-bit 3.3 V ADC.
What it buys youAn acquisition contract with independent error budgets.

A field team faces an unresolved physical question: How can a clean sample still arrive at the wrong time? They must answer it before changing clock drift on the real device. Predict the direction first.

See the relationship before changing it

The figure reads from left to right. The blue card is clock drift. The middle card applies this page's relationship. The green card is minimum raw rate. Walk the arrows once: set the input, apply the rule, then read the result with its unit.

The retained audit below checks several chapter fixtures. This added model holds every other chapter fixture fixed, so the numeric fixture does not switch without explanation.

Clock drift changes minimum raw rate An input card leads through the page relationship to the minimum raw rate result. SET INPUT ONE CONTROL APPLY RULE predict calculate check units READ RESULT
Walk the arrows. Clock error grows with elapsed time. Sample value error follows different formulas, so both budgets must be closed independently.

Derive the baseline in four named moves

  1. 1

    Name the input. The chapter baseline for clock drift is 50.

  2. 2

    Name the relationship. fs,min=2(500)=1,000 Hz; raw interval=1.00 ms 100 Hz summary interval=10.00 ms 3,600 sx50/1,000,000=0.180 s=180 ms; 180/10=18 samples 3.3 V/4,096=0.806 mV; qrms=0.233 mV; SNR=74.0 dB

  3. 3

    Substitute the chapter fixture. Set clock drift to 50. The page ledger gives minimum raw rate as 1000 Hz.

  4. 4

    Read the result. Keep Hz beside the value. Use it only inside the technical boundary on this page.

Predict, then change clock drift

Try Predict the direction of minimum raw rate. Move one control, calculate, then check your prediction.

50
Chapter baseline
Minimum raw rate

Observe Clock error grows with elapsed time. Sample value error follows different formulas, so both budgets must be closed independently. Reset the control to 50 and compare minimum raw rate.

Explain Only clock drift moves here. The other chapter fixtures remain fixed.

Check yourself

What should you do before trusting a moved-control result?
Answer: Predict its direction, apply the shown relationship, keep the units, and reset to the worked baseline.
What does this small model leave out?
Answer: Only clock drift moves. Field effects named in the page's technical boundary stay fixed.

Honesty note. This teaching model changes only clock drift. It replays the chapter fixture; it is not a field prediction.

1. Separate value from time

An ADC code says how large the measured voltage was. A timestamp says when it was measured. One can be accurate while the other is wrong.

Data Dora: A precise timestamp on an aliased sample records the wrong value very neatly.

2. Name every algebra move

1

Double the input bandA 500 Hz band needs at least 1,000 Hz raw sampling.

2

Invert the summary rate100 Hz means 1/100 s=10 ms between summaries.

3

Scale parts per millionDrift=time×ppm/1,000,000.

4

Count missed intervalsSample error=drift/interval.

5

Audit voltage roundingq=Vref/2ᴺ and qrms=q/√12.

3. Reproduce the chapter case

fs,min=2(500)=1,000 Hz; raw interval=1.00 ms
100 Hz summary interval=10.00 ms
3,600 s×50/1,000,000=0.180 s=180 ms; 180/10=18 samples
3.3 V/4,096=0.806 mV; qrms=0.233 mV; SNR=74.0 dB

The 18-sample phase error is added to the ADC error; it does not replace it.

4. Try the oscillator drift

TryMove the clock from 5 to 100 ppm and watch elapsed milliseconds turn into misplaced 100 Hz samples.

Clock drift
Minimum raw rate
Raw interval
Summary interval
ADC levels
ADC step
ADC RMS noise
Ideal ADC SNR
One-hour drift
Misalignment

ObserveAt 50 ppm the clock drifts 180.0 ms in one hour, which spans 18.00 summary intervals. Halving ppm halves both timing outputs, but the ADC outputs do not move.

ExplainClock error grows with elapsed time. Sample value error follows different formulas, so both budgets must be closed independently.

Technical boundaries.

This ledger uses constant oscillator error and ideal sample spacing.

Clock
Real drift changes with temperature, ageing, jitter, and synchronization traffic
Sampling
The 500 Hz band is catalog-typical, not measured chapter evidence
ADC
The ideal noise equation omits analogue and reference errors

Measure source clocks, spectrum, anti-alias response, and end-to-end event-time error.

5. Decide which fix applies

Use an anti-alias filter and sufficient raw rate for value integrity. Use clock synchronization and event timestamps for alignment. Use enough buffer and an explicit policy for delay and outage.

6. Keep the acquisition record

Record sensor bandwidth, raw and summary rates, ADC configuration, clock source, sync interval, event and receive times, buffer size, loss policy, owner, and retest trigger.

7. Check yourself

Why does a 500 Hz band need 1,000 Hz sampling?
Answer: Nyquist requires at least twice the highest retained frequency.
How does 180 ms become 18 samples?
Answer: A 100 Hz stream has 10 ms intervals, and 180/10=18.
Does clock sync repair an aliased waveform?
Answer: No. It aligns timestamps but cannot reconstruct frequency content lost before sampling.
Honesty boundary.

The summary and clock values come from the chapter; acquisition bandwidth and ADC are labelled assumptions.

100 Hz, 50 ppm, 180 ms, 18 samples
The chapter's timing example
500 Hz raw band
A catalog-typical condition-monitoring assumption
12-bit, 3.3 V
A catalog-typical ADC example

Correct, not complete: a trustworthy stream also needs buffer, network, clock, and sensor validation.

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