Math Bridge: ADC Quantisation and Ideal SNR

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Math BridgeElectronicsStruggle-friendly runway

How does one extra ADC bit shrink the staircase error?

Connect ADC bit depth to levels, step size, rounding error, RMS quantisation noise, and ideal SNR.

Eddie, the electronics guideEddie guides
The one targetTurn ADC bit depth into a complete ideal quantisation ledger.
The chapter caseA 12-bit ADC using the chapter’s 3.3 V reference.
What it buys youA visible limit for step size, noise, and ideal SNR before real errors are added.

A technician must decide whether ideal code width is safe before changing adc resolution on the real device. The result is unresolved until the rule and units are checked. Predict the direction first.

See the relationship before changing it

The figure reads from left to right. The blue card is adc resolution. The middle card applies this page's rule. The green card is ideal code width. Walk the arrows once: set the input, apply the rule, then read the result with its unit.

The retained audit below checks several chapter fixtures. This model keeps those stated values fixed and changes only adc resolution, so the numeric fixture does not switch without explanation.

ADC resolution changes ideal code width An input card leads through the rule ADC code width = 3,300 mV / 2^bits to the ideal code width result. INPUT PAGE INPUT APPLY THE RULE predict calculate check units OUTPUT RESULT
Walk the arrows. Each added bit halves the ideal voltage staircase step.

Derive the baseline in four named moves

  1. 1

    Name the input. The chapter baseline is 12 bits.

  2. 2

    Name the relationship. ADC code width = 3,300 mV / 2^bits

  3. 3

    Substitute with units. 3,300 / 2^12 = 0.8057 mV

  4. 4

    Read the result. Keep the unit beside the value. Use it only inside the technical boundary on this page.

Predict, then change adc resolution

Try Predict the direction of ADC code width = 3,300 mV / 2^bits. Test another adc resolution, then compare ideal code width.

12 bits
Chapter baseline
Ideal code width

Observe Each added bit halves the ideal voltage staircase step. Reset adc resolution to 12 and compare ideal code width.

Explain Each added bit halves the ideal voltage staircase step.

Check yourself

What should you do before trusting a moved-control result?
Answer: Predict its direction, apply the shown relationship, keep the units, and reset to the worked baseline.
What does this small model leave out?
Answer: Only adc resolution moves here. Field effects named in the technical boundary stay fixed.

Honesty note. This teaching model changes only adc resolution. It is not a field prediction.

1. Start with the physical story

An ADC must replace a smooth voltage with one numbered stair. More bits create more stairs, so each stair and its rounding error become smaller.

Eddie: Follow one quantity at a time; every displayed result comes from the same ledger.

2. Name every algebra move

1

Count the levelsRaise 2 to the bit depth N.

2

Find one stepDivide the reference voltage by the number of levels.

3

Bound roundingThe nearest-code error can reach half a step.

4

Turn a bound into RMS noiseDivide one step by the square root of 12.

5

Express the ideal signal gapUse 6.02N+1.76 dB for a full-scale sine.

3. Reproduce the chapter case

levels=2^12=4096
q=3.3/4096=0.8057 mV
peak error=q/2=0.4028 mV
RMS noise=q/√12=0.2326 mV
ideal SNR=6.02(12)+1.76=74.0 dB

The arithmetic stays visible so that units and assumptions can be checked before the result is used.

4. Try one real input

TryMove the bit depth. Predict whether one extra bit halves the voltage step.

Bits
Levels
Step size
Peak rounding error
RMS noise
Sensor-equivalent RMS
Signal/noise amplitude
Ideal SNR

ObserveEach added bit doubles the level count and halves step, peak error, and RMS noise.

ExplainThe ideal SNR rises by about 6.02 dB per bit because doubling the signal-to-noise amplitude ratio adds about 6 dB.

Technical boundaries.

This transparent ledger reproduces the named chapter case.

Input
The uniform-error model assumes a busy input that crosses many codes.
Converter
Missing codes, DNL, INL, reference noise, and aperture jitter are outside this ledger.
System
Sensor and analogue-front-end errors must be added in their own units.

Correct, not complete: this ledger does not qualify an ADC, reference, sensor front end, or measurement chain.

5. Use the result in the design

Choose enough nominal bits for the required voltage step, then budget reference noise, front-end noise, nonlinearity, and effective number of bits separately.

6. Record the evidence state

Record reference voltage, nominal and effective bits, input range, sensor sensitivity, measured noise, bandwidth, and temperature.

7. Check yourself

Why does one more bit halve q?
Answer: Because 2^(N+1) has twice as many levels across the same reference span.
Is ±q/2 the same as RMS noise?
Answer: No. It is the peak nearest-code bound; the uniform-error RMS value is q/√12.
Does 74.0 dB describe a real 12-bit ADC?
Answer: Only as an ideal full-scale-sine ceiling. Real reference, timing, thermal, and linearity errors reduce it.
Honesty boundary.

This transparent ledger reproduces the named chapter case.

Input
The uniform-error model assumes a busy input that crosses many codes.
Converter
Missing codes, DNL, INL, reference noise, and aperture jitter are outside this ledger.
System
Sensor and analogue-front-end errors must be added in their own units.

Correct, not complete: this ledger does not qualify an ADC, reference, sensor front end, or measurement chain.

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