Which Stage Is Really the Bottleneck?

Ada re-derives this chapter’s own numbers step by step, at full precision

foundations
math-foundations
calculation-audit
ux-design
Ada ADA · CALCULATION AUDIT

Which Stage Is Really the Bottleneck?

The chapter’s voice-interface latency sums to 1,095 ms — just past the 1,000 ms “It’s broken” cliff — and calls the 220 ms cloud ASR round-trip “the biggest bottleneck.” Yet audio capture at 350 ms and TTS at 310 ms are both larger. This audit ranks the stages to ask which stage is really the bottleneck, and finds ASR is the most fixable, not the biggest.

Companion to the chapter Interface Design: Multimodal Interaction — every number here comes from that chapter.

Ada: The latency budget sums to 1,095 ms, and the chapter calls the 220 ms cloud ASR round-trip “the biggest bottleneck.” The total is right, but “biggest” needs a careful eye, because the largest stage and the most fixable stage are not the same thing.

First the sum, and where it lands:

  • 80 + 350 + 220 + 75 + 60 + 310 = 1,095 ms
  • The perception table marks >1000 ms as “It’s broken,” so the baseline sits just 1,095 - 1,000 = 95 ms over the cliff

Now rank the stages by size:

  • Audio capture 350 ms (32% of the budget), the largest single stage
  • TTS response 310 ms (28%)
  • Cloud ASR 220 ms (20%)

So ASR is only the third largest stage. Audio capture and TTS together are 350 + 310 = 660 ms, 60% of the whole budget. The reason ASR still deserves first attention is that it is the biggest avoidable cost, a pure network round-trip you can delete, whereas audio capture is partly irreducible (you must wait for the speaker to stop). And that reframing pays off: removing the ASR round-trip alone (220 -> 45, saving 175 ms) brings the total to 1,095 - 175 = 920 ms, already back under the “broken” cliff without touching anything else. The full 520 ms optimum is a 52.5% cut, but the audit’s point is that the first, cheapest move, killing the round-trip, is the one that rescues the experience; the rest is polish toward the more ambitious <800 ms comfort target.

Every number above is taken from the chapter’s own material and re-derived step by step.