DAC and PWM Output Calculation Audit

Ada re-derives this chapter’s own numbers step by step, at full precision

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ADA · CALCULATION AUDIT

DAC and PWM Output Calculation Audit

An ESP32-style 8-bit DAC on a 3.3 V rail steps every 12.94 mV, a 12-bit DAC roughly 16 times finer, while a 75% PWM duty on 5 V averages to 3.75 V and a common 0.22 uF RC filter settles in about 11 ms. Code steps, duty fractions, and RC time constants are easy to blur into one story. This audit keeps each in its own lane and asks which physical limit — step size, duty average, or settling delay — each number actually belongs to.

Companion to the chapter DAC and PWM Output — every number here comes from that chapter.

A DAC code, a PWM duty cycle, and an RC filter all turn numbers into physical voltage. The audit is to keep the code range, reference voltage, duty fraction, and time constant separate until the final result.

See the relationship before changing it

The figure reads from left to right. The blue card is pwm duty. The middle card applies this page's rule. The green card is ideal average voltage. Walk the arrows once: set the input, apply the rule, then read the result with its unit.

The retained audit below checks several chapter fixtures. This model keeps those stated values fixed and changes only pwm duty, so the numeric fixture does not switch without explanation.

Walk the arrows. Duty sets the ideal average while the load and RC filter set ripple and settling.

Derive the baseline in four named moves

1
Name the input. The chapter baseline is 75 %.
2
Name the relationship. average voltage = 5 V x duty / 100
3
Substitute with units. 5 x 75 / 100 = 3.75 V
4
Read the result. Keep the unit beside the value. Use it only inside the technical boundary on this page.

Predict, then change pwm duty

Try Predict the direction of average voltage = 5 V x duty / 100. Test another pwm duty, then compare ideal average voltage.

Observe Duty sets the ideal average while the load and RC filter set ripple and settling. Reset pwm duty to 75 and compare ideal average voltage.

Explain Duty sets the ideal average while the load and RC filter set ripple and settling.

Check yourself

What should you do before trusting a moved-control result?

Answer: Predict its direction, apply the shown relationship, keep the units, and reset to the worked baseline.

What does this small model leave out?

Answer: Only pwm duty moves here. Field effects named in the technical boundary stay fixed.

Try

Use Calculate for 75% PWM at 5 V and a 10 kohm, 0.22 uF RC filter.

Observe

Check reports 3.75 V ideal average, 72.3 Hz cutoff, and about 11 ms settling to 99%.

Explain

Duty sets average PWM voltage, whereas RC time constant filters ripple by trading a lower 72.3 Hz bandwidth for slower response.

Technical boundaries

For the output filter case, excluded from this fixed arithmetic are switching-device losses, load transients, DAC non-linearity, timer jitter, or real filter-component tolerances.

1. DAC resolution is a voltage step, not just a bit label. For the ESP32-style 8-bit, 3.3 V example in this chapter, the endpoint code range is 0 through 255.

maximum code = 2⁸ - 1 = 255; endpoint step = 3.3 V / 255 = 0.0129412 V = 12.94 mV

midscale example = 128 * (3.3 V / 255) = 1.65647 V, rounded at the end to 1.66 V

2. More bits shrink the voltage step exponentially. A 12-bit DAC has 4096 levels, so it is roughly 16 times finer than an 8-bit DAC over the same reference range.

12-bit endpoint step = 3.3 V / 4095 = 0.000805861 V = 0.805861 mV

level ratio = 4096 / 256 = 16; endpoint-step ratio = 12.94 mV / 0.805861 mV = 16.06

Check	Arithmetic	What it proves
75% PWM at 5 V	5 V * 0.75 = 3.75 V	PWM average voltage follows duty fraction before any load or filter physics changes the waveform.
1 kHz period	1 / 1000 Hz = 0.001 s = 1 ms	The switching period is much shorter than the filter settling time in the worked example.
100 Hz design capacitor	1 / (2 * pi * 10000 ohm * 100 Hz) = 0.000000159 F = 0.159 uF	This is the calculated capacitor for a 100 Hz cutoff with a 10k ohm resistor.
Common 0.22 uF part	1 / (2 * pi * 10000 ohm * 0.22 uF) = 72.3 Hz	The rounded component choice lowers the cutoff, improving smoothing while slowing response.
Settling time	5 * 10000 ohm * 0.22 uF = 0.011 s = 11 ms	The filter needs about 11 ms to reach roughly 99% of a new target.

Audit rule: keep endpoint-code calculations, average-voltage calculations, and filter time-constant calculations in their own lanes. A clean design states which physical effect each number belongs to before comparing DAC and PWM options.

Every number above is taken from the chapter’s own material and re-derived step by step.